Design and CAD methodologies for low power gate-level monolithic 3D ICs

Abstract

In a gate-level monolithic 3D IC (M3D), all the transistors in a single logic gate occupy the same tier, and gates in different tiers are connected using nano-scale monolithic inter-tier vias. This design style has the benefit of the superior power-performance quality offered by flat implementations (unlike block-level M3D), and zero total silicon area overhead compared to 2D (unlike transistor-level M3D). In this paper we develop, for the first time, a complete RTLto-GDSII design flow for gate-level M3D. Our tool flow is based on commercial tools built for 2D ICs and enhanced with our 3D-specific methodologies. We use this flow along with a 28nm PDK to build layouts for the OpenSPARC T2 core. Our simulations show that at the same performance, gate-level M3D offers 16% total power reduction with 0% area overhead compared to commercial quality 2D IC designs.

Optimization of dynamic power consumption in multi-tier gate-level monolithic 3D ICs

“…GMI can reuse existing 2D standard cells and timing/power libraries. In addition, [4] proposed a design methodology using 2D placement tools for the design of gate-level monolithic 3D ICs and achieved almost 20% wirelength reduction and 16% power reduction. Thus, GMI is a prospective design methodology with respect to the design effort and the quality (wirelength, timing, and power) of 3D ICs.…”

“…The 3D global placement algorithm presented in [4] works as follows. First, they determine a downscaling ratio s based on the ratio between the width (w 2D ) of the 2D layout and the width (w 3D ) of a target 3D layout of the design (s = w 3D /w 2D ).…”

“…HPWLi ≤ HPWLi + δi (4) where HPWL i is the half-perimeter wirelength of net i before non-uniform scaling, HPWL i is the HPWL of net i after nonuniform scaling, and δ i is a relaxation factor, which we use to allow some delay margin for each net.…”

“…A simple, but effective way to place cells in 3D is to use an existing 2D placement tool to generate a high-quality 2D placement result, downscale the cell locations by a constant scaling ratio, and remove cell overlaps by partitioning [4]. This methodology, namely a uniform-scaling-based placement algorithm, scales down the length of each net by almost the same ratio as the constant scaling ratio, thereby reducing wirelength and dynamic power consumption.…”

Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications

“…A design flow for gate-level 3D VLSI was presented in [5]. First, the width and height of the 2D chip are shrunk by 1/ √ 2 to create a 3D footprint.…”