Design and development of the first single-chip full-duplex OC48 traffic manager and ATM SAR SoC

Khan, Aurangzeb; Patel, Krishna Kumar; Aurora, A.; Raza, Ali; Parruck, B.; Bagchi, Ann D.; Ghosh, Abhishek; Litinsky, Boris; Hong, Eunki; Zhao, Enhai; Ngo, J.; Ko, K.Y.; Singh, Leena; Arnaudov, P.; Wu, Pi-An; Ramakrishnan, R.; Zecharia, R.; Channabasappa, S.; Kumar, Smita; Wattal, S.; Wang, T.; Joshi, U.; Golan, Z.; Luo, Zunning; Le, Duc-Ngoc; Ahmed, Irfan; Chiu, Fu-Chien; Chow, Kingsum; Furuzono, H.; Ge, D.; Li, Min; Mueller, M.; Nguyen, Son Truong; Nguyen, T.; Saito, Junichi; Shen, Junda; Todesco, A.; Tsou, A.; Wang, Demin; Yang, Steven; Yu, J.; Zhong, X.

doi:10.1109/cicc.2003.1249354

Cited by 8 publications

(3 citation statements)

References 4 publications

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“…In many cases, the TM is a hard core attached to a flexible processing pipeline and represents a parameterizable TM IP core. To date, little research has been published on complete TM architectures with the only work on specific TM functions in ASIC [Chiussi et al 2001;Khan et al 2003] or FPGA [Fereydouni-Forouzandeh and Otmane 2004;IDT 2005;Krishnamurthy et al 2004]. The focus here is to derive a modular architecture that utilizes common building blocks to create the complete TM configuration.…”

Section: Current Tm Solutionsmentioning

confidence: 99%

A Scalable and Programmable Modular Traffic Manager Architecture

O’Neill

Woods

Marshall

et al. 2011

ACM Trans. Reconfigurable Technol. Syst.

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A key issue in the design of next-generation Internet routers and switches will be provision of Traffic Manager (TM) functionality in the datapaths of their high-speed switching fabrics. A new architecture that allows dynamic deployment of different TM functions is presented. By considering the processing requirements of operations such as policing and congestion, queuing, shaping, and scheduling, a solution has been derived that is scalable with a consistent programmable interface. Programmability is achieved using a function computation unit which determines the action (e.g., drop, queue, remark, forward) based on the packet attribute information and a memory storage part. Results of a Xilinx Virtex-5 FPGA reference design are presented.

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Section: Current Tm Solutionsmentioning

confidence: 99%

A Scalable and Programmable Modular Traffic Manager Architecture

O’Neill

Woods

Marshall

et al. 2011

ACM Trans. Reconfigurable Technol. Syst.

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“…Khan et al [26] proposed a traffic management solution implemented with dedicated circuits that can support 5 Gb/s with full duplex capabilities. Khan showed all the design steps up to the physical realization of a TM circuit.…”

Section: Traffic Managersmentioning

confidence: 99%

A High-Speed, Scalable, and Programmable Traffic Manager Architecture for Flow-Based Networking

2019

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In this paper, we present a programmable and scalable traffic manager (TM) architecture, targeting requirements of high-speed networking devices, especially in the software-defined networking context. This TM is intended to ease the deployability of new architectures through field-programmable gate array (FPGA) platforms and to make the data plane programmable and scalable. Flow-based networking allows treating traffic in terms of flows rather than as a simple aggregation of individual packets, which simplifies scheduling and bandwidth allocation for each flow. Programmability brings agility, flexibility, and rapid adaptation to changes, allowing to meet network requirements in real-time. Traffic management with fast queuing and reduced latency plays an important role to support the upcoming 5G cellular communication technology. The proposed TM architecture is coded in C++ and is synthesized with the Vivado High-Level Synthesis tool. This TM is capable of supporting links operating beyond 40 Gb/s, on the ZC706 board and XCVU440-FLGB2377-3-E FPGA device from Xilinx, while achieving 80 Gb/s and 100 Gb/s throughput, respectively. The resulting placed and routed design was tested on the ZC706 board with its embedded ARM processor controlling table updates.INDEX TERMS Traffic manager (TM), flow-based networking, data plane, high-level synthesis (HLS), field-programmable gate array (FPGA).

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“…TM hardware architectures have been derived with dedicated functions for ATM QoS and cell processing [13]. The FPGA -based MATMUNI system concentrates on network-on-chip rather than TM aspects [14].…”

Section: Traffic Manager Backgroundmentioning

confidence: 99%

An On-Demand Queue Management Architecture for a Programmable Traffic Manager

Zhang

Woods

Marshall

2012

IEEE Trans. VLSI Syst.

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A queue manager (QM) is a core traffic management (TM) function used to provide per-flow queuing in access and metro networks; however current designs have limited scalability. An on-demand QM (OD-QM) which is part of a new modular field-programmable gate-array (FPGA)-based TM is presented that dynamically maps active flows to the available physical resources; its scalability is derived from exploiting the observation that there are only a few hundred active flows in a high speed network. Simulations with real traffic show that it is a scalable, cost-effective approach that enhances per-flow queuing performance, thereby allowing per-flow QM without the need for extra external memory at speeds up to 10 Gbps. It utilizes 2.3%-16.3% of a Xilinx XC5VSX50t FPGA and works at 111 MHz.Index Terms-Field programmable gate arrays (FPGAs), queue management (QM), traffic manager (TM).

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Design and development of the first single-chip full-duplex OC48 traffic manager and ATM SAR SoC

Cited by 8 publications

References 4 publications

A Scalable and Programmable Modular Traffic Manager Architecture

A Scalable and Programmable Modular Traffic Manager Architecture

A High-Speed, Scalable, and Programmable Traffic Manager Architecture for Flow-Based Networking

An On-Demand Queue Management Architecture for a Programmable Traffic Manager

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