2020
DOI: 10.1016/j.mejo.2020.104844
|View full text |Cite|
|
Sign up to set email alerts
|

Design and implementation of robust and low-cost SRAM PUF using PMOS and linear shift register extractor

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
2
0

Year Published

2021
2021
2024
2024

Publication Types

Select...
6
1

Relationship

1
6

Authors

Journals

citations
Cited by 7 publications
(2 citation statements)
references
References 7 publications
0
2
0
Order By: Relevance
“…In [ 86 ], to improve the stability of responses in SRAM PUF, PMOS is added as an SRAM power switch to guarantee an ns-level (the time it takes for VDDs to increase from zero to a supply voltage VDD) of SRAM cell, which can decrease the power-up time and drop the probability of bit flips. When the chip is powered on, the SRAM power switch is turned on by default.…”
Section: Pufmentioning
confidence: 99%
“…In [ 86 ], to improve the stability of responses in SRAM PUF, PMOS is added as an SRAM power switch to guarantee an ns-level (the time it takes for VDDs to increase from zero to a supply voltage VDD) of SRAM cell, which can decrease the power-up time and drop the probability of bit flips. When the chip is powered on, the SRAM power switch is turned on by default.…”
Section: Pufmentioning
confidence: 99%
“…We obtained the PUF reliability [5] parameter to take into account the effect of start-up time and temperature. The considered temperature range was −20 • C to +60 • C and the start-up time was varied more than one order of magnitude according to [37,38]. Results were 97.1% and 98.3% respectively, suggesting that the percentages of cells listed in Table 3, which as stated by [35] correspond to the least influenced by external disturbances, will be largely unaffected by these factors.…”
mentioning
confidence: 99%