Design and Investigation of Gate-to-Gate Passive Interconnections for SFQ Logic Circuits

Hashimoto, Y.; Yorozu, Shinichi; Kameda, Yusuke; Fujimaki, Akira; Terai, Hirotaka; Yoshikawa, Nobuyuki

doi:10.1109/tasc.2005.847487

Cited by 24 publications

(11 citation statements)

References 14 publications

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“…For example, at 100 GHz, the address timing interval is just 10 ps, which leaves little room for the same variations in propagation delay that we observed in Figure 5. Our SPICE simulations show bias margins ranging from ±24% (at 20 GHz) to ±13% (at 100 GHz), which are well above the widely accepted ±10% threshold 33 .…”

Section: Circuits Description and Performance Evaluationsupporting

confidence: 67%

Pulsar: A Superconducting Delay-Line Memory

Tzimpragos¹,

Volk²,

Wynn³

et al. 2022

Preprint

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Logic and fabrication advancements have renewed interest in superconductor electronics for energy-efficient computing and quantum control processors. One of the most challenging obstacles ahead is the lack of a scalable superconducting memory technology. Here, we present a superconducting delay line memory based on Passive Transmission Lines built with high kinetic inductors. The developed memory system is fully superconducting; operates at speeds ranging from 20 GHz to 100 GHz with ±24% and ±13% bias margins, respectively; and exhibits data densities in the 10s of Mbit/cm 2 with the MIT Lincoln Laboratory SC2 fabrication process. Moreover, its circulating nature allows the miniaturization of control circuitry, the elimination of data splitting and merging, and the inexpensive implementation of both sequential-access and content-addressable memories. Further advancements to high kinetic inductor fabrication processes indicate even greater data densities of 100s of Mbit/cm 2 and beyond.

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Section: Circuits Description and Performance Evaluationsupporting

confidence: 67%

Pulsar: A Superconducting Delay-Line Memory

Tzimpragos¹,

Volk²,

Wynn³

et al. 2022

Preprint

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“…The logic gates are magnetically shielded from the bias current by the ground plane because a superconductor is the best magnetic shield material. The fifth layer is a shielding layer between the logic gates and the sixth layer which creates a pattern for the X-direction passive transmission line (PTL) [13], in which SFQ pulses are transmitted. The seventh layer shields the X-direction and the eighth layer forms the Y -direction PTL.…”

Section: Advanced Processmentioning

confidence: 99%

Current status and future prospect of the Nb-based fabrication process for single flux quantum circuits

Hidaka

Nagasawa

Satoh

et al. 2006

Supercond. Sci. Technol.

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The Superconductivity Research Laboratory has successfully fabricated large quantities of single flux quantum (SFQ) large scale integrated circuits, including several thousands of Josephson junctions (JJs). Using a J c = 2.5 kA cm −2 process in which the number of Nb layers was four and the minimum JJ size was 2 µm square. We developed a new advanced fabrication process that produced a J c = 10 kA cm −2 , nine Nb layers and a minimum JJ size of 1 µm square. The increase in the number of Nb layers was achieved by using a planarization technique. The target of our next generation process is a J c = 40 kA cm −2 with a 0.5 µm square for the minimum junction size. This specification will be achieved by using advanced semiconductor technologies. This process will enable SFQ circuits to be produced with one million JJs on a chip and achieve a clock frequency greater than 100 GHz.

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“…For this reason, PTLs have been developed and used in a lot of SFQ circuits. [19][20][21][22][23][24][25] However, to date, wiring with PTLs has been very inflexible and not practical for use in SFQ integrated circuits since only a microstrip-line (MSL) structure has been used. There are two reasons why introducing two or more wiring structures is very difficult.…”

Section: Introductionmentioning

confidence: 99%

Flexible Superconducting Passive Interconnects with 50-Gb/s Signal Transmissions in Single-Flux-Quantum Circuits

Yamada¹,

Ryoki²,

Fujimaki³

et al. 2006

jjap

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We have developed a very flexible wiring technique of passive transmission lines (PTLs) in single-flux-quantum (SFQ) circuits. For high flexibility, we introduced two types of wiring structures of strip lines (SLs) and microstrip lines (MSLs) using the fabrication process which has four metal layers. The SLs and MSLs are realized using the second and fourth metal layers as signal lines, respectively, from the bottom (the other two metal layers are used as ground planes). We also introduced via-holes for transmission between the SL and MSL. For solving the problem of impedance mismatch on complicated discontinuous sections such as joints [between the driver(receiver) and the end of SLs(MSLs)] and via-holes, we optimized the structures of these discontinuous sections and evaluated propagation properties to ensure high-speed transmission of SFQ pulses. We tested the transmission of SFQ pulses through SLs/MSLs including more than 50 via-holes, one of the most complicated lines in actual designs. We confirmed the good propagation properties of SFQ pulses up to 50 Gb/s with sufficiently wide bias margins of ±20% to be used in practical designs.

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Design and Investigation of Gate-to-Gate Passive Interconnections for SFQ Logic Circuits

Cited by 24 publications

References 14 publications

Pulsar: A Superconducting Delay-Line Memory

Pulsar: A Superconducting Delay-Line Memory

Current status and future prospect of the Nb-based fabrication process for single flux quantum circuits

Flexible Superconducting Passive Interconnects with 50-Gb/s Signal Transmissions in Single-Flux-Quantum Circuits

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