Design and Optimization of 22 nm Gate Length High-k/Metal gate NMOS Transistor

A.H, Afifah Maheran; Menon, P. Susthitha; Ahmad, Ibrahim; Shaari, Sahbudin; Elgomati, H. A.; Salehuddin, F.

doi:10.1088/1742-6596/431/1/012026

Cited by 15 publications

(14 citation statements)

References 10 publications

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“…Implementing the L9 Orthogonal Array of Taguchi Method experiment [7], the results of the device's threshold voltage (V th ) are analysed. In order to get the best design of the target value (V th ) which is also known as the nominal value, there are important steps that must be considered.…”

Section: Resultsmentioning

confidence: 99%

“…SNR of NTB quality characteristics is used to achieve the targeted V th where the intended results needs to be exactly or closer to the target value. The SNR for NTB,  can be expressed as [7] where  is the mean value and  is the variance in the experiment. In order to choose the best level of the process parameters, one must choose the highest mean value of each process parameter.…”

Section: A Analysis For 22nm Pmos Devicementioning

confidence: 99%

“…With added noise factors called signal-to-noise ratio (SNR), process parameter variability using Taguchi method becomes more reliable. In this experiment, since the objective is to achieve a decent target value which is also called as nominal value, the SNR (Nominal-the-Best, NTB) analysis is utilized [7]. In addition, the analysis of variance (ANOVA) was executed in order to identify the most significant value of the process parameters.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method

Maheran

Menon

Shaari

et al. 2014

2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)

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This paper provides the enhancement of 22nm planar PMOS transistor technology through downscaling, design parameter simulation and optimization process. The scaled down device is optimized for its process parameter variability using Taguchi method. The aim is to find the best combination of fabrication parameters in order to achieve the target value of the threshold voltage (V th ). A combination of high permittivity material (high-k) and metal gate is utilized simultaneously in replacing the conventional SiO 2 /Poly-Si technology. For this, Titanium dioxide (TiO 2 ) was used as the high-k material and tungsten silicide (WSi x ) was used as the metal gate. The simulation results show that the optimal threshold voltage (V th ) of -0.289 V ± 12.7% is achieved in accordance to the ITRS 2012 specifications. This provides a benchmark towards the fabrication of 22 nm planar PMOS in future work.

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Section: Resultsmentioning

confidence: 99%

Section: A Analysis For 22nm Pmos Devicementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method

Maheran

Menon

Shaari

et al. 2014

2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)

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“…Replacing the SiO2 with a high-k material allows increased gate capacitance [3]. The electrical characteristics of the device performance are analyzed with several of high-k materials and the gate oxide thickness is scaled to get same Equivalent Oxide Thickness (EOT) defined as equation 1: (1) Where: TM1 and TM2 are the physical thickness of metalsoxides M1 and M2, εM1 and εM2 are their relatives dielectrics constants respective, εSiO2 is relative dielectric of the SiO2.…”

Section: High-k Dielectricmentioning

confidence: 99%

Effects of High-k Dielectrics with Metal Gate for Electrical Characteristics of SOI TRI-GATE FinFET Transistor

Rahou¹,

Bouazza²,

Bouazza³

2016

J. Nano- Electron. Phys.

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In this paper, we present the results of a 3D-numerical simulation of SOI TRI-GATE FinFET transistor. 3D-device structure, based on technology SOI (Silicon-On-Insulator) is described and simulated by using SILVACO TCAD tools and we compare the electrical characteristics results for Titanium Nitride (TiN) fabricated on Al2O3 (k ~ 9), HfO2 (k ~ 20) and La2O3 (k ~ 30) gate dielectric. Excellent dielectric properties such as high-k constant, low leakage current, threshold voltage and electrical characteristics were demonstrated. The implementation of high-k gate dielectrics is one of several strategies developed to allow further miniaturization of microelectronic components. From the simulation result; it was shown that HfO2 is the best dielectric material with metal gate TiN, which giving better subthreshold swing (SS), drain-induced barrier lowing (DIBL), leakage current Ioff and Ion/Ioff ratio.

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“…A higher dielectric constant material is introduced to replace SiO2 which allows thicker dielectric to be deposited to reduce leakage without electrical thickness penalties [11][12]. Commonly, a substantial sum of studies has been issued on the prediction of leakage current and leakage power by numerous researchers, along with the study on the performance of high-K materials [13][14][15][16][17][18]. High dielectric constant, large band gap with favorable band alignment, low interface state density and good thermal stability are amongst the best characteristics to have for the gate dielectric.…”

Section: Introductionmentioning

confidence: 99%

Enhanced performance of 19 single gate MOSFET with high permittivity dielectric material

Roslan

Salehuddin

Zain

et al. 2020

IJEECS

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In this research, the performance of the 19 nm single gate MOSFET is enhanced through the implementation of the high permittivity dielectric material. The MOSFET scaling trends necessities in device dimensions can be satisfied through the implementation of the high-K dielectric materials in place of the SiO2. Therefore, the 19 nm n-channel MOSFET device with different High-K dielectric materials are implemented and its performance improvement has also been analysed. Virtual fabrication is exercised through ATHENA module from Silvaco TCAD tool. Meanwhile, the device characteristic was utilized by using an ATLAS module. The aforementioned materials have also been simulated and compared with the conventional gate oxide SiO2 for the same structure. At the end, the results have proved that Titanium oxide (TiO2) device is the best dielectric material with a combination of metal gate Tungsten Silicides (WSix). The drive current (ION) of this device (WSix/TiO2) is 587.6 µA/um at 0.534 V of threshold voltage (VTH) as opposed to the targeted 0.530 V predicted, as well as a relatively low IOFF that is obtained at 1.92 pA/µm. This ION value meets the minimum requirement predicted by International Technology Roadmap for Semiconductor (ITRS) 2013 prediction for low performance (LP) technology.

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Design and Optimization of 22 nm Gate Length High-k/Metal gate NMOS Transistor

Cited by 15 publications

References 10 publications

Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method

Effect of process parameter variability on the threshold voltage of downscaled 22nm PMOS using taguchi method

Effects of High-k Dielectrics with Metal Gate for Electrical Characteristics of SOI TRI-GATE FinFET Transistor

Enhanced performance of 19 single gate MOSFET with high permittivity dielectric material

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