Design and optimization of high voltage analog and digital circuits built in a standard 5 V CMOS technology

Abstract

This paper presents a new family of highvoltage (HV) analog and digital circuits which arefully compatible with a standard 5V CMOS technology, without any process change. On the basis of several circuits, it is shown that HV design can be classified in three categories, for which a common design methodology can be identified. Detailed circuit sizing as well as measurements illustrate the performance achieved with this technique.

An Integrated Chip High-Voltage Power Receiver for Wireless Biomedical Implants

“…Prior work published is for low-voltage applications below 1.8 V. However, the proposed design includes an LV-HV cascading [25] scheme to overcome the input voltage limitation and contain a higher supply voltage. The implemented circuit schematic of the reference voltage and bias current generator [14] is shown in Figure 4.…”

“…Therefore, in stability analysis, a pole P 2 , is generated by the large gate capacitance of the pass transistor in addition to the low-frequency pole P 1 , created by the output capacitance, which degrades the stability. Various approaches have been employed to address the issue [3,10,14,[25][26][27][28][29][30]. In [26][27][28], large quiescent current consumption is required in the intermediate buffer stage to ensure stability, thereby degrading the current efficiency of the LDO under low load conditions.…”

“…HV input voltage LDOs are reported in [3,10,14,25,27] for operating voltages in the range of 10-50 V. In [10], the input operating voltage is in the range of 10-30 V, but the design utilizes a pre-regulator module to initially step down the voltage for supplying power to the error amplifier stage.…”

“…The proposed LDO uses a current buffer compensation topology, with a low impedance buffer, to attain stability for varying load conditions; Figure 6. The error amplifier is realized by a folded-cascode structure, with cascaded LV-HV transistors to contain high input voltage [25]. The pass device is a p-type HV transistor with a rated maximum voltage of 45 V. The resistor feedback network is constituted by R F B1 and R F B2 , with capacitors C1 and C2 connected in parallel to R F B1 and R F B2 , respectively, for reducing high frequency noise [29].…”

High-voltage devices for 0.5-μm standard CMOS technology

“…The impact of this request is the motivation for adding high-voltage modules in low-voltage CMOS technologies. A solution to this problem uses smart voltage extension (SVX) technique which allows the implementation of high-voltage complementary devices without any modifications of the process steps [1], [2]. In fact, the SVX technique, as successfully applied in 2-µm technology, consists of using the standard n-well of the process as the n-drift of the high-voltage NMOS (HVNMOS) and the "p-tub channel stop" implant as the p-drift of the high-voltage PMOS (HVPMOS).…”