Design and Optimization of Program and Restore Operations in CMOS-Compatible Nonvolatile Latch

2012

Abstract:We explore a dual-band fractional-N PLL synthesizer with 3.5 mW, 5 μsec settling time and 15 μsec start-up time in 0.18 μm CMOS technology. The power consumption is minimized through the design efforts in LC-VCO design to maximize the quality factor of an integrated inductor up to 6.1 at 866 MHz and minimize the VCO gain by a capacitor tuning technique with an on-chip nonvolatile memory and the proper choice of varactor. Measured results of a prototype fractional-N PLL satisfy the required settling and start-up times, and indicate that the phase noises at 10 kHz and 100 KHz offset are −108.7 dBc/Hz and −98.3 dBc/Hz, respectively, and the reference spurious level is −81.6 dBc.

Section: Resultsmentioning

confidence: 99%

A 3.5mW 5µsec settling time dual-band fractional-N PLL synthesizer

2012

“…In this paper, we present the principle, design, application and evaluation results of a prototype 32-bit 16-program-cycle NV-M for analog circuit calibration in a standard 0.18 µm CMOS [4].…”

Section: Introductionmentioning

confidence: 99%

A 32-bit 16-program-cycle nonvolatile memory for analog circuit calibration in a standard 0.18µm CMOS

2012

Abstract:We propose a 32-bit 16-program-cycle nonvolatile memory fabricated in a standard 0.18 µm CMOS technology based on a channel hot-electron trapping at the transistor gate sidewall. Its target application is calibration of RF/analog circuits for multiband/multimode communication systems, that demands in-field multiple-time programmability and data select-ability. The issue of the one-time programmability in the proposed memory cell is overcome by the addressing memory cell array, and the promised reliability is observed through the optimization of program and restore operations. The developed nonvolatile memory is applied to a dual-band PLL synthesizer with an area overhead of 8.5%.

“…Moreover, since the optimum value of V CTRL at the onset of the closed-loop operation is not V DD /2 but is susceptible to process variation of VCO varactors, this variation is individually calibrated through the optimization of the open-loop V CTRL with V CTRL setting code, D DAC , and a followed DAC to linearize the VCO operation. A 32-bit 16-program-cycle NV-M fabricated in a standard CMOS can provide these calibration data with the minimum fabrication cost overhead [5].…”

Section: Introductionmentioning

confidence: 99%

Fractional-N PLL synthesizer with 15µsec start-up time by on-chip nonvolatile memory

2012

Abstract:We propose a fractional-N PLL synthesizer with 15 μsec start-up time featuring an open-loop VCO capacitor coarse setting and subsequent VCO control voltage setting technique with a nonvolatile memory, which can eliminate the frequency detection and VCO coarse tuning sequence used in conventional start-up acceleration techniques. The on-chip nonvolatile memory fabricated in a standard CMOS technology stores the predetermined calibration data to overcome the process variations in VCO capacitors and varactors. A prototype PLL is designed in a standard 0.18 μm CMOS technology with die size of 950 μm x 515 μm and 10.4% area overhead of the acceleration circuits, and presents the measured start-up time of 14.6 μsec.