Design and realisation of a new hardware efficient IP core for the 1-D discrete Fourier transform

Chien, Charles; Lin, Chun-Liang; Yang, C-M.; Guo, Jiun-In

doi:10.1049/ip-cds:20041172

Cited by 4 publications

(1 citation statement)

References 19 publications

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“…In particular, multipliers consume much silicon area of FPGA because they are implemented with adder trees. Various implementation proposals have been made to save area by removing these multipliers [ 7 – 10 ].…”

Section: Algorithm To Hardwarementioning

confidence: 99%

An Efficient Pipeline Wavefront Phase Recovery for the CAFADIS Camera for Extremely Large Telescopes

Magdaleno

Rodríguez

Rodríguez-Ramos

2009

Sensors

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In this paper we show a fast, specialized hardware implementation of the wavefront phase recovery algorithm using the CAFADIS camera. The CAFADIS camera is a new plenoptic sensor patented by the Universidad de La Laguna (Canary Islands, Spain): international patent PCT/ES2007/000046 (WIPO publication number WO/2007/082975). It can simultaneously measure the wavefront phase and the distance to the light source in a real-time process. The pipeline algorithm is implemented using Field Programmable Gate Arrays (FPGA). These devices present architecture capable of handling the sensor output stream using a massively parallel approach and they are efficient enough to resolve several Adaptive Optics (AO) problems in Extremely Large Telescopes (ELTs) in terms of processing time requirements. The FPGA implementation of the wavefront phase recovery algorithm using the CAFADIS camera is based on the very fast computation of two dimensional fast Fourier Transforms (FFTs). Thus we have carried out a comparison between our very novel FPGA 2D-FFTa and other implementations.

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Section: Algorithm To Hardwarementioning

confidence: 99%