Design and Realization of GaAs Digital Circuit for Mixed Signal MMIC Implementation in AESA Applications

Abstract

A complete design flow starting from the technological process development up to the fabrication of digital circuits is presented. The aim of this work is to demonstrate the GaAs Enhancement/Depletion (E/D) double stop-etch technology implementation feasibility for digital applications, aimed at mixed signal circuit integration. On the basis of the characterization of small E/D devices with different Gate peripheries, developed by the SELEX-SI foundry, and the analysis of several GaAs-based logical families, the most suitable logic for the available technology has been selected. Then, simple test vehicles (level shifters, NOR logic gates and D Flip-Flops) have been designed, realized, and measured to validate the design strategy applied to the GaAs E/D process. These logical circuits are preliminary to the design of a more complex serial-to-parallel converter, to be implemented onto the same chip together with RF analog blocks, such as stepped attenuators and phase shifters.

GaAs-Based Serial-Input-Parallel-Output Interfaces for Microwave Core-Chips

“…As shown in Figure 3b, the inverter gate is simply a common-source transistor, with the load resistor replaced by a D-mode FET in the E/D version. As anticipated, during the 80s and 90s E-mode-only logic was practically never exploited, due to the large area occupation and power dissipation issues related to resistive pull-ups [22,28], while nowadays both versions are exploited: active pull-ups have the advantage of non-linear resistance response varying from very small to very high values depending on the drain-source voltage, while resistive pull-ups are beneficial for power consumption, if properly sized, and, above all for yield. Resistors, in fact, are less subject to process variations than active devices, and in any case, the sensitivity of the logic gate to their exact value is much more relaxed with respect to the sensitivity to, e.g., the transistor threshold voltage.…”

Compact 4‐bit GaAs Ku‐band core chips for phased arrays

“…Several logic families were proposed based on E‐mode pHEMTs. Among the families, the direct coupled FET logic (DCFL) in Figure is used. Figure shows the basic DCFL logic gates such as, (a) the inverter, (b) the two‐input NOR, and (c) the three‐input NOR gates based on DCFL.…”

“…Core chips based on CMOS and SiGe BiCMOS technologies are promising because both CMOS and SiGe BiCMOS technologies provide an easy integration with high‐speed digital circuits and have advantages in cost and mass production over GaAs. However, from a point of view of the current states of the technologies, the noise figure of an amplifying device based on GaAs technology is generally superior to that based on CMOS, and SiGe BiCMOS technologies, which is the one of the crucial factors in the application of core chips to a phased array. Furthermore, most current phased arrays do not need core chips with highly complex digital circuits.…”

A 7.5–9 GHz GaAs Two-Channel Multi-Function Chip

“…In contrast to other logic families (e.g., two-phase dynamic FET logic (TDFL), source-coupled FET logic (SCFL), pseudo-complementary FET logic (PCFL), feedback FET logic (FFL), etc. ), the direct-coupled FET logic (DCFL) is the most commonly used logic style and is chosen in this design, which has compact topology and low power dissipation [11].…”