In this paper, an overview of recently reported low-noise amplifiers (LNAs), designed, and fabricated in GaN technology is provided, highlighting their noise performance together with high-linearity and high-robustness capabilities. Several SELEX-ES GaN monolithic technologies are detailed, providing the results of the noise characterization and modeling on sample devices. An in-depth review of three LNAs based on the 0.25-µm GaN HEMT process, marginally described in previous publications, is then presented. In particular, two robust and broadband 2-18-GHz monolithic microwave integrated circuit (MMIC) LNAs are designed, fabricated, and tested, exhibiting robustness to over 40-dBm input power levels; an X-band MMIC LNA, suitable for synthetic aperture radar systems, is also designed and realized, for which measurement results show a noise figure ∼2.2 dB with an associated gain >25 dB and robustness up to 41-dBm input power level.

In the framework of silicon (Si) technology, evolution towards high-frequency analog applicationswhich involves innovative solutions such as SiGe BiCMOS and FinFET deviceswide bandgap semiconductors grown on Si substrates are likely to represent a valid option in those cases wherever high-power handling and low noise figures are required. Although such active devices have been extensively investigated in the last years, much of interest has been devoted in developing nonlinear models for high-power applications, whereas reliable noise models still lack, in particular, the validity of traditional (i.e. equivalent temperature-based) approaches for noise modeling of wide bandgap devices has not been sufficiently probed yet.In this contribution, a quite general, black box noise model of active devices is proposed and applied to a family of gallium nitride-on-Si high-electron-mobility transistors fabricated by Selex ES. The model is based on a polynomial approximation of the device correlation matrix and does not require that an accurate small-signal equivalent circuit is available; instead, it can be extracted from multifrequency source pull data. Experimental results demonstrate that a typical behavior of the noise parameters is obtained, both versus frequency and gate periphery.

No abstract

No abstract

A complete design flow starting from the technological process development up to the fabrication of digital circuits is presented. The aim of this work is to demonstrate the GaAs Enhancement/Depletion (E/D) double stop-etch technology implementation feasibility for digital applications, aimed at mixed signal circuit integration. On the basis of the characterization of small E/D devices with different Gate peripheries, developed by the SELEX-SI foundry, and the analysis of several GaAs-based logical families, the most suitable logic for the available technology has been selected. Then, simple test vehicles (level shifters, NOR logic gates and D Flip-Flops) have been designed, realized, and measured to validate the design strategy applied to the GaAs E/D process. These logical circuits are preliminary to the design of a more complex serial-to-parallel converter, to be implemented onto the same chip together with RF analog blocks, such as stepped attenuators and phase shifters.