Design and Verification Environment for High-Performance Video-Based Embedded Systems

Abstract

In this dissertation, a method and a tool to enable design and verification of computation demanding embedded vision-based systems is presented. Starting with an executable specification in OpenCV, we provide subsequent refinements and verification down to a system-on-chip prototype into an FPGA-Based smart camera. At each level of abstraction, properties of image processing applications are used along with structure composition to provide a generic architecture that can be automatically verified and mapped to the lower abstraction level. The result is a framework that encapsulates the computer vision library OpenCV at the highest level, integrates Accelera's System-C/TLM with UVM and QEMU-OS for virtual prototyping and verification and mapping to a lower level, the last of which is the FPGA. This will relieve hardware designers from time-consuming and error-prone manual implementations, thus allowing them to focus on other steps of the design process. We also propose a novel streaming interface, called Component Interconnect and Data Access (CIDA), for embedded video designs, along with a formal model and a component composition mechanism to cluster components in logical and operational groups that reduce resource usage and power consumption.

Universal Verification Platform and Star Simulator for Fast Star Tracker Design

“…There are already works where computer vision applications successfully employed UVM-SystemC as a design aid tool. In [ 9 ], a verification environment using SystemC and UVM was created for computational demanding video-based embedded systems. A system design starting with an executable specification in C++ and the computer vision library OpenCV ( ) was verified.…”