Design for testability in digitally-corrected ADCs

Mangelsdorf, Chris; Lee, S.-H.; Martin, M.N.; Malik, Hassan; Fukuda, Takahiro; Matsumoto, Hiroki

doi:10.1109/isscc.1993.280079

Cited by 17 publications

(2 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…During the next 10 cycles, the SHA repeatedly samples recycled output signals from the MDAC. The flash ADC transmits 2 b digital data to the DCL during each cycle and nonlinear errors such as offsets and clock feed-through in the SHA, the MDAC, and the flash ADC are digitally corrected in the DCL [1], [10]. By using 11 clock cycles from a 2.2 MHz input system clock, the ADC operates at a 200 kS/s conversion rate.…”

Section: Proposed Adc Architecturementioning

confidence: 99%

A 12 b 200 kS/s 0.52 mA 0.47 mm2 Algorithmic A/D Converter for MEMS Applications

Kim

Choi

Lee

et al. 2008

IEICE Transactions on Electronics

Self Cite

View full text Add to dashboard Cite

This work describes a 12 b 200 kS/s 0.52 mA 0.47 mm 2 ADC for sensor applications such as motor control, 3-phase power control, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with a recycling signal path to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels employs a folded-cascode amplifier to achieve a required DC gain and a high phase margin. A 3-D fully symmetric layout with critical signal lines shielded reduces the capacitor and device mismatch of the multiplying D/A converter while switched-bias power-reduction circuits minimize the power consumption of analog amplifiers. Current and voltage references are integrated on chip with optional off-chip voltage references for low glitch noise. The down-sampling clock signal selects the sampling rate of 200 kS/s and 10 kS/s with a further reduced power depending on applications. The prototype ADC in a 0.18 µm n-well 1P6M CMOS process demonstrates a maximum measured DNL and INL within 0.40 LSB and 1.97 LSB and shows a maximum SNDR and SFDR of 55 dB and 70 dB at all sampling frequencies up to 200 kS/s, respectively. The ADC occupies an active die area of 0.47 mm 2 and consumes 0.94 mW at 200 kS/s and 0.

show abstract

Section: Proposed Adc Architecturementioning

confidence: 99%

A 12 b 200 kS/s 0.52 mA 0.47 mm2 Algorithmic A/D Converter for MEMS Applications

Kim

Choi

Lee

et al. 2008

IEICE Transactions on Electronics

Self Cite

View full text Add to dashboard Cite

show abstract

“…The key advantages are that these techniques reduce the sensitivity of the linearity of such ADC's to offsets in their comparators and offsets in their interstage analog processing. One disadvantage of this approach that is not well known is that the digital-correction logic is difficult to test indirectly (that is, without direct access to both its inputs and outputs) during normal ADC operation [4], [5]. This is because the correction logic eliminates redundancy by converting the set of its uncorrected inputs into a smaller set of corrected outputs.…”

Section: Introductionmentioning

confidence: 99%