Design, modeling and characterization of embedded capacitor networks for mid-frequency decoupling in semiconductor systems

Muthana, P.; Swaminathan, Madhavan; Tummala, Rao; Raj, P. Markondeya; Engin, Ege; Wan, Lixi; Bhattacharya, Swapan Kumar

doi:10.1109/isemc.2005.1513592

Cited by 13 publications

(6 citation statements)

References 6 publications

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“…It can be observed that frequency band over which the target impedance can be met with the above mentioned decoupling elements is To target the frequency band from 60MHz to 120MHz shown in the circled area in Figure 4, embedded package capacitors can be used. The advantage of using embedded capacitors has been previously shown in [3,4]. The placement of embedded capacitors to target the desired frequency response is critical and has been highlighted in [4].…”

Section: Figurel:crosssectionofthepackagementioning

confidence: 99%

“…The advantage of using embedded capacitors has been previously shown in [3,4]. The placement of embedded capacitors to target the desired frequency response is critical and has been highlighted in [4]. It is critical that the embedded capacitors are placed under the die shadow and that the number of vias and the configuration are chosen so that the desired frequency band is targeted.…”

Section: Figurel:crosssectionofthepackagementioning

confidence: 99%

“…The trade-off of increasing the onchip capacitance could be a decrease in the logic density or additional manufacturing technology investments. Therefore, an alternate approach could be to provide most of the high frequency decoupling from embedded package capacitors as shown in [3,4]. The advantage would be an increase in the amount of real estate for logic on-chip and increase in the capacitance that can be provided for decoupling from the package.…”

Section: Figurel:crosssectionofthepackagementioning

confidence: 99%

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Analysis of Embedded Package Capacitors for High Performance Components

Muthana¹,

Matoglu

Pham

et al. 2006

2006 IEEE Electrical Performane of Electronic Packaging

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The ever increasing power requirements of processors and application specific integrated circuits (ASICs) impose stringent requirements on the design of Power Distribution Networks (PDNs). This paper highlights a power analysis methodology and discusses the decoupling requirements of high performance components. The advantages of embedded package capacitors in core and 1/0 decoupling will be highlighted.Introduction-The increase in power densities of high end microprocessors and ASICs creates a design challenge for the power distribution networks of these systems. This can be attributed to the rise in the number of transistors on-chip which has increased the active and leakage power through the technology nodes. The increase in the frequency of the operation of the clock has led to an increase in bandwidth over which the system PDN requirements are to be met. Another challenge is in the interconnect data rate. The bit rate on interconnects is increasing rapidly. For proper operation of circuits it is required that the jitter due to the switching noise be minimized. Therefore, the design of PDNs has become more important and difficult due to the increasing bandwidth of the switching noise.A good PDN provides low impedance wherever current transients exist. This impedance is decided by the core operating voltage and the average current drawn by the component. The impedance that the PDN must be designed to meet is called the target impedance. The relationship between the target impedance, voltage and the average current drawn by the component is [1]

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Section: Figurel:crosssectionofthepackagementioning

confidence: 99%

Section: Figurel:crosssectionofthepackagementioning

confidence: 99%

Section: Figurel:crosssectionofthepackagementioning

confidence: 99%

See 1 more Smart Citation

Analysis of Embedded Package Capacitors for High Performance Components

Muthana¹,

Matoglu

Pham

et al. 2006

2006 IEEE Electrical Performane of Electronic Packaging

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“…However, in order for the EBG structure to be effective at our frequencies of interest, a large area is required. Thirdly, embedded capacitors composed of a high dielectric constant core, thin-film insulator have been used to store electric charges and suppress the SSN [4], but these usually provide relatively poor isolation at high frequency. To satisfy a compact system-in-package requirements, the PDN must supply DC power with low impedance and high immunity to noise over a wideband of frequencies with small form factor.…”

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confidence: 99%

π -type lowpass filter for wideband noise suppression in small size package

Liao

Cao

et al. 2010

Electron. Lett.

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The design and implementation of a moral p-type lowpass filter for wideband suppression of simultaneous switching noise in a small size, mixed signal system-in-package is reported. The filter consists of a continous conductive layer, a segmented conductive layer and a thin-film insulator having high dielectric constant between the two to replace the conventional power/ground planes in a package. From 0.55 to 4 GHz, the insertion loss of testing points, with a distance of only 4 mm, is measured to be greater than 240 dB for this filter. The proposed structure is suitable for low-cost, wideband noise supression in a highly integrated mixed signal system-in-package.Introduction: In a high-speed mixed signal system-in-package, the design of a low-impedance and low-noise power distribution network (PDN) has become a major challenge owing to simultaneous switching noise (SSN) or ground bounce noise (GBN). The SSN causes voltage fluctuations that can couple within the PDN to disturb nearby sensitive circuits. The resonances excited by GBN will cause the electromagnetic interference (EMI) problem. Compared with a PDN on a PCB, the PDN on package has its own characteristics: smaller size and higher density. Noise abatement is particularly demanding in small packages where space is premium.There are several approaches for isolating the SSN. First, adding surface mount decoupling capacitors is restricted by the equivalent serial inductance (ESL) above several hundreds of MHz [1], and there is commonly not enough room to place many decoupling capacitors in the package. Secondly, in recent years, the concept of using electromagnetic bandgap (EBG) structures on the power planes has been studied [2, 3]. The EBG can omnidirectionally reduce noise with a bandstop behaviour. However, in order for the EBG structure to be effective at our frequencies of interest, a large area is required. Thirdly, embedded capacitors composed of a high dielectric constant core, thin-film insulator have been used to store electric charges and suppress the SSN [4], but these usually provide relatively poor isolation at high frequency. To satisfy a compact system-in-package requirements, the PDN must supply DC power with low impedance and high immunity to noise over a wideband of frequencies with small form factor. We describe a PDN meeting these requirements based on a p-type lowpass filter.

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“…To reduce the effect of the plane spreading inductance, the lower ESL capacitors were placed closer to the BGA balls. Embedded capacitors within the package were used to target the frequency band from IOOMHz to 2GHz as discussed above and in [9]. For frequencies above 2GHz, on-chip capacitance has been used to meet the target impedance.…”

mentioning

confidence: 99%

Mid frequency decoupling using embedded decoupling capacitors

Muthana

Swaminathan

Engin

et al.

IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, 2005.

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Surface Mount Technology (SMT) decoupling capacitors fail to provide decoupling above 100MHz. This paper presents the use of embedded thin film capacitors to provide decoupling in the mid frequency range from 100MHz to 2GHz. On-chip capacitance provides decoupling above 2GHz. The effect of chip, package and board capacitors on the performance of digital systems is analyzed taking into account the parasitic effects of power/ground planes, vias and solder balls. A synthesis and selection methodology for embedded package capacitors is also presented. Introduction The Intemational Roadmap for Semiconductors (ITRS) has projected an increase in the power consumption of microprocessors for future technology nodes [1]. For chips with a feature size of 90nm, supply voltage of 1.2V and chip size of 140mm2, the power dissipation is expected to be 84W. Table I shows a variation of different microprocessor parameters for cost performance applications for the 90, 65 and 45nm nodes. The power delivery network (PDN) provides the power supply to the processor. If improperly designed this network could be a major source of noise, such as ground bounce and electromagnetic interference (EMI) [2]. A methodology for designing a good PDN is to define a target impedance for the network that should be met over a broad frequency band [3]. This parameter can be computed by assuming a 5% allowable ripple in the voltage supply and a 50% switching current in the rise and fall time of the processor clock [2]. Target impedance can be calculated as z Vddx0.05,where Vdd is the core voltage of the processor and I is the current drawn by the microprocessor from the PDN. The target impedance listing for the 90, 65 and 45nm technology nodes is listed in Table 1. The current can be calculated from the power and voltage as P=VddI.(2) Table 1: Target impedance through technology nodes Year Feature size (nm) Power (W) Vdd (V) Current (A) Target Impedance (mQ) 2004 90 84 1.2 70 1.7 2007 65 103.6 0.9 115.11 0.781 2010 45 119 0.6 198.33 0.302As the processor is powered through the board and the package, the design of the PDN in both these levels is extremely important. Decoupling capacitors play a very important role in the PDN as they act as charge providers for the switching circuits. The target impedance has to be met over a broad frequency band; the low frequency, mid frequency and high frequency capacitors need to be appropriately placed to meet this requirement. This paper will analyze the performance of mid frequency band decoupling capacitors in the PDN. SMT capacitors provide good decoupling up to around 100MHz. Figure 1 shows the response of 3 SMT capacitors placed at a port of reference (solid line) in a 10cm by 10cm plane. The response of the same capacitors placed 10mm away from the port is also shown as dashed lines in Figure 1. It can be clearly seen that the performance of capacitors is dependent on its placement on the plane. The sensitivity of capacitors performance to its placement is also highlighted in [4]. This trend is further magnifi...

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Design, modeling and characterization of embedded capacitor networks for mid-frequency decoupling in semiconductor systems

Cited by 13 publications

References 6 publications

Analysis of Embedded Package Capacitors for High Performance Components

Analysis of Embedded Package Capacitors for High Performance Components

π -type lowpass filter for wideband noise suppression in small size package

Mid frequency decoupling using embedded decoupling capacitors

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