Mid frequency decoupling using embedded decoupling capacitors

Abstract

Surface Mount Technology (SMT) decoupling capacitors fail to provide decoupling above 100MHz. This paper presents the use of embedded thin film capacitors to provide decoupling in the mid frequency range from 100MHz to 2GHz. On-chip capacitance provides decoupling above 2GHz. The effect of chip, package and board capacitors on the performance of digital systems is analyzed taking into account the parasitic effects of power/ground planes, vias and solder balls. A synthesis and selection methodology for embedded package capacitors is also presented. Introduction The Intemational Roadmap for Semiconductors (ITRS) has projected an increase in the power consumption of microprocessors for future technology nodes [1]. For chips with a feature size of 90nm, supply voltage of 1.2V and chip size of 140mm2, the power dissipation is expected to be 84W. Table I shows a variation of different microprocessor parameters for cost performance applications for the 90, 65 and 45nm nodes. The power delivery network (PDN) provides the power supply to the processor. If improperly designed this network could be a major source of noise, such as ground bounce and electromagnetic interference (EMI) [2]. A methodology for designing a good PDN is to define a target impedance for the network that should be met over a broad frequency band [3]. This parameter can be computed by assuming a 5% allowable ripple in the voltage supply and a 50% switching current in the rise and fall time of the processor clock [2]. Target impedance can be calculated as z Vddx0.05,where Vdd is the core voltage of the processor and I is the current drawn by the microprocessor from the PDN. The target impedance listing for the 90, 65 and 45nm technology nodes is listed in Table 1. The current can be calculated from the power and voltage as P=VddI.(2) Table 1: Target impedance through technology nodes Year Feature size (nm) Power (W) Vdd (V) Current (A) Target Impedance (mQ) 2004 90 84 1.2 70 1.7 2007 65 103.6 0.9 115.11 0.781 2010 45 119 0.6 198.33 0.302As the processor is powered through the board and the package, the design of the PDN in both these levels is extremely important. Decoupling capacitors play a very important role in the PDN as they act as charge providers for the switching circuits. The target impedance has to be met over a broad frequency band; the low frequency, mid frequency and high frequency capacitors need to be appropriately placed to meet this requirement. This paper will analyze the performance of mid frequency band decoupling capacitors in the PDN. SMT capacitors provide good decoupling up to around 100MHz. Figure 1 shows the response of 3 SMT capacitors placed at a port of reference (solid line) in a 10cm by 10cm plane. The response of the same capacitors placed 10mm away from the port is also shown as dashed lines in Figure 1. It can be clearly seen that the performance of capacitors is dependent on its placement on the plane. The sensitivity of capacitors performance to its placement is also highlighted in [4]. This trend is further magnifi...

Through Silicon Capacitor co-integrated with TSV as an efficient 3D decoupling capacitor solution for power management on silicon interposer

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“…The PDN should have an impedance of less than the target impedance over a frequency range of DC to hundreds of MHz [7] [8]. In general, impedance peaks appear in the frequency range from a few MHz to GHz, owing to circuit resonance from the capacitance and the effective inductance of the PDN; thus, a good PDN design must maintain this impedance peak below the target impedance [9] [10].…”

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“…Applications such as DC-DC converters and Power Distribution Networks (PDN) decoupling require high capacitance density (up to 100 nF/mm²) placed at the vicinity of the dies to avoid noise and ensure reliable operating system [1][2]. Meeting this capacitance densities value implies the use of a large die area.…”