Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies

Lee, Jri; Chiang, Po-Jui; Peng, Pen-Jui; Chen, Li‐Yang; Weng, Chih-Chi

doi:10.1109/jssc.2015.2433269

Cited by 119 publications

(28 citation statements)

References 19 publications

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“…In addition, for emulating actual link performance, impairments such as device package (pkg) and crosstalk are necessarily added into the link system in a form of S-parameter [12], [13]. Figure 2 gives a typical DFE for PAM4 system [14]. It can be seen that three separate slicers with different threshold voltages (+V th , 0, −V th ) are used to generate a 3-bit thermometer code (d U , d M , d B ), respectively, which will be converted to two NRZ signals (d MSB , d LSB ) by a decoder.…”

Section: Architecturementioning

confidence: 99%

DFE Error Propagation and FEC Interleaving for 400GbE PAM4 Electrical Lane

Zhan

Zhang

2020

IEICE Trans. Electron.

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This paper analyzes the effect of error propagation of decision feedback equalizer (DFE) for PAM4 based 400 Gb/s Ethernet. First, an analytic model for the error propagation is proposed to estimate the probability of different burst error length due to error propagation for PAM4 link system with multi-tap TX FFE (Feed Forward Equalizer) + RX DFE architecture. After calculating the symbol error rate (SER) and bit error rate (BER) based on the probability model, the theoretical analysis about the impact of different equalizer configurations on BER is compared with the simulation results, and then BER performance with FEC (Forward Error Correction) is analyzed to evaluate the effect of DFE error propagation on PAM4 link. Finally, two FEC interleaving schemes, symbol and bit interleaving, are employed in order to reduce BER further and then the theoretical analysis and the simulation result of their performance improvement are also evaluated. Simulation results show that at most 0.52 dB interleaving gain can be achieved compared with non-interleaving scheme just at a little cost in storing memory and latency. And between the two interleaving methods, symbol interleaving performs better compared with the other one from the view of tradeoff between the interleaving gain and the cost and can be applied for 400 Gb/s Ethernet.

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Section: Architecturementioning

confidence: 99%

DFE Error Propagation and FEC Interleaving for 400GbE PAM4 Electrical Lane

Zhan

Zhang

2020

IEICE Trans. Electron.

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“…Typically, in a high‐speed wireline transmitter (TX), the PAM‐4 signals are generated by combining the most significant bit (MSB) and least significant bit (LSB) signals [3]. Therefore, a simulation environment is built in Fig.…”

Section: Analysis Of Pam‐4 Signal Distortionsmentioning

confidence: 99%

Study on the effects of distortions and common‐mode noise in high‐speed PAM‐4 systems

2018

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A study of different distortions in high-speed differential PAM-4 signals, including the linear distortions, i.e. amplitude mismatch, channel skew and bandwidth mismatch, and the non-linear distortion, i.e. the mismatch between rising and falling edges is presented. It is observed that only the non-linear distortion introduces a large common-mode (CM) noise at the double Nyquist frequency, which causes electromagnetic interference (EMI) in high-speed serial links. At last, Monte-Carlo simulations are performed to investigate the impact of signal distortions on the EMI-related CM noise.

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“…Another modification is about Rx DFE slicer levels [8][9]. We need to add TSL, MSL and BSL (top/middle/bottom slicer level) to the reserved parameter list.…”

Section: Ami Model Extension For Pam4 Signalingmentioning

confidence: 99%

IBIS-AMI Based PAM4 Signaling and FEC Technique for 25 Gb/s Serial Link

Zhan¹,

Hu²,

Zhang³

2017

Lecture Notes in Computer Science

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This paper investigates Input/Output Buffer Information Specification Algorithmic Model Interface (IBIS-AMI) model extension for 25Gb/s PAM4 (4-level Pulse Amplitude Modulation) serial link to improve the development efficiency. By using the ADS (Advanced Design System) Channel Simulator, the effects of device package, jitter and crosstalk on the actual performance are studied at first. Then, for forward error correction (FEC) technique, the bit error rate (BER) performance and the bathtub curves are analyzed in detail. Simulation results show that device package, jitter and crosstalk can make the link performance worse. And much better performance can be obtained by using the combination of equalization and FEC techniques compared with using the equalization technique separately.

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Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies

Cited by 119 publications

References 19 publications

DFE Error Propagation and FEC Interleaving for 400GbE PAM4 Electrical Lane

DFE Error Propagation and FEC Interleaving for 400GbE PAM4 Electrical Lane

Study on the effects of distortions and common‐mode noise in high‐speed PAM‐4 systems

IBIS-AMI Based PAM4 Signaling and FEC Technique for 25 Gb/s Serial Link

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