Design of a 10-Gb/s burst-mode optical packet receiver module and its demonstration in a WDM optical switching network

Nishizawa, Hideki; Yamada, Yoshiaki; Habara, K.; Ohyama, T.

doi:10.1109/jlt.2002.800325

Cited by 30 publications

(10 citation statements)

References 15 publications

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“…Furthermore, this value of T OH implies a 60 bit header. In [6], a 10 Gb/s optical packet receiver is demonstrated, using a 40 bit long preamble. Therefore, the remaining 20 bits will carry packet information: 5 bits are reserved for packet length (expressed in time slots, for a maximum value of 2 5 −1 = 31 time slots), and the remaining 15 bits for the destination ES address (up to a maximum of 2 15 edge systems).…”

Section: Network Architecturementioning

confidence: 99%

Sharing tunable wavelength converters in AWG-based IP optical switching nodes

Pattavina

Rebughini

Sipone

2005

2nd International Conference on Broadband Networks, 2005.

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This paper deals with the design of an optical packet switch architecture adopting an arrayed waveguide grating device for packet routing. Due to the high cost of optical components, the node structure proposed here is equipped with a pool of tunable wavelength converters fully shared among all input channels. An analytical model is developed that allows us to evaluate the packet loss performance of a bufferless version of such structure. The model accuracy is assessed by means of computer simulation.Index Terms-All-optical networks, arrayed waveguide grating (AWG), tunable wavelength converter (TWC), internet protocol (IP), optical packet switching (OPS).

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Section: Network Architecturementioning

confidence: 99%

Sharing tunable wavelength converters in AWG-based IP optical switching nodes

Pattavina

Rebughini

Sipone

2005

2nd International Conference on Broadband Networks, 2005.

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“…Moreover, this value of T H implies a 60 bit header. In [6] a 10 Gb/s optical packet receiver is demonstrated, using a 40 bit-long preamble. Therefore, the remaining 20 bits will carry packet information: 5 bits are reserved for packet length (expressed in time-slots, for a maximum value of 2 5 − 1 = 31 time-slots), and the remaining 15 bits for the destination ES address (up to a maximum of 2 15 edge-systems).…”

Section: Network Architecturementioning

confidence: 99%

Architectures and performance of awg-based optical switching nodes for ip networks

Bregni

Pattavina

Vegetti

2003

IEEE J. Select. Areas Commun.

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In order to support the continuous growth of transmission capacity demand, optical packet switching technology is emerging as a strong candidate, promising to allow fast dynamic allocation of WDM channels, combined with a high degree of statistical resource sharing. This work addresses the design of optical switch architectures, based on previous proposals available in the technical literature that use an arrayed waveguide grating (AWG) device to route packets. Since the port number of currently available AWGs is a limiting factor, we propose two new modified structures which better exploit the switching capability of this component in the wavelength domain.Since a limited hardware complexity is a key requirement for all-optical switches, due to the high cost of optical components, these different node configurations are compared in terms of complexity. Traffic performance of these new structures in a full optical packet switching scenario is also examined.

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“…Circuit designers wishing to measure the lock acquisition time of a clock and data recovery (CDR) circuit will also benefit from this research. An in-depth discussion of BMRs is beyond the scope of this text; the interested reader is referred to [1] [3][7]- [10] for more information.…”

Section: Introductionmentioning

confidence: 99%

Test setup for optical burst-mode receivers

Faucher

Mony

Plant

Proceedings of the Lightwave Technologies in Instrumentation and Measurement Conference, 2004.

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This paper proposes a test setup that can accurately measure the lock acquisition time of conventional and burst mode receivers subjected to phase, frequency, or amplitude steps. This work will be useful to network architects and circuit designers who wish to know with precision how many bits a receiver needs to acquire lock. The technique for measuring lock acquisition time, or preamble length, is based on an acceptable BER for the payload. Measurement results for the lock acquisition time of two commercially available OC-48 receiver chips will be presented.Index Terms -Burst switching, optical receivers, packet switching, phase detection, phase locked loops.

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Design of a 10-Gb/s burst-mode optical packet receiver module and its demonstration in a WDM optical switching network

Cited by 30 publications

References 15 publications

Sharing tunable wavelength converters in AWG-based IP optical switching nodes

Sharing tunable wavelength converters in AWG-based IP optical switching nodes

Architectures and performance of awg-based optical switching nodes for ip networks

Test setup for optical burst-mode receivers

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