Design of a clockless MSP430 core using mixed asynchronous design flow

Shin, Ziho; Oh, Myeong‐Hoon; Lee, Jeong-Gun; Kim, Hag Young; Kim, Young Woo

doi:10.1587/elex.14.20170162

Cited by 4 publications

(6 citation statements)

References 16 publications

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“…The other is to provide compatibility with existing synchronous languages and EDA tools. [19,20,21] redesign asynchronous standard cell (ASTC) libraries in NCL [22] style. After synchronous synthesis, they translate the netlists to ASTC.…”

Section: Asynchronous Methodologymentioning

confidence: 99%

Snake: An asynchronous pipeline for ultra-low-power applications

Zhu

Bai

et al. 2019

IEICE Electron. Express

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Voltage scaling is an effective technique for ultra-low-power applications. However, PVT variation degrades the robust of traditional synchronous pipelines severely when voltage scales into the sub-threshold region. In this paper, we propose a register-based bundled-data asynchronous pipeline that can operate robustly in sub-threshold, called Snake. By looping the match delay line, the Snake halves the design overhead compared to other asynchronous pipelines. We also propose a practical asynchronous design methodology which is compatible with commercial EDA and needs only a few modifications to synchronous design flow.Monte-Carlo SPICE simulation shows that the pipelined multiplier applying the proposed techniques operates stably in 0.2 V and achieves minimum power 1.3 nW in 0.2 V, minimum energy 1.07 pJ per cycle in 0.3 V. It provides 6.7 times superiority over synchronous baseline design with 22% area overhead. Comparison with other works in the state of art shows the proposed techniques are quite competitive.

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Section: Asynchronous Methodologymentioning

confidence: 99%

Snake: An asynchronous pipeline for ultra-low-power applications

Zhu

Bai

et al. 2019

IEICE Electron. Express

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“…And for the address, inputted address is translated to memory address then, related to the Req and Ack signals, the respected data is delivered. To check its functionality in the real system, we implement the entire system on to the Spartan-3 FPGA and it runs benchmark programs [34], when every module is passed the timing simulation.…”

Section: Resultsmentioning

confidence: 99%

“…The host PC was used for downloading the bitstream file to target FPGA through the JTAG interface as well as timing simulation for before implementing the designed core. To check the functionality of designed core, we run the emulator [35] as the reference core on the host PC and it executes same benchmark program [34]. The host PC monitors output signals of designed core.…”

Section: Resultsmentioning

confidence: 99%

Implementation of an Asynchronous Micro-controlleron the Commercial FPGA

Shin¹,

Oh²,

Kwon³

et al. 2017

IJCTE

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Abstract-An asynchronous circuit design methodology has been introduced as a novelty approach to future digital system design. Nevertheless, in order to implement the asynchronous circuit, there are various limitations. Especially, for the implementation on a commercialized field programmable gate array (FPGA), the vendors and design tools mainly support only synchronous circuit design. In this paper, we propose design techniques for implementing the asynchronous circuit on the commercial FPGA using the provided design tool. Then, with the proposed design techniques, we designed an asynchronous micro-controller based onaTIMSP430 instruction set architecture (ISA).We observe that the asynchronous core consumes lower power than the synchronous one. In addition, the asynchronous core also shows much more durability under conditions of unstable power supplies compared to the synchronous counterpart.Index Terms-Asynchronous circuit, AFSM, bounded delay, FPGA.

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“…Clock skew and hence clock delay balancing are difficult to manage due to technology scaling, as the clock signal needs to arrive at the same time at all storage elements [46][47][48][49]. Moreover, synchronous circuits invest 40% and more of its power in clock distribution [50,51], and as the design grows in complexity, additional delay units are required to tune the delay from the clock source to the flip-flops/latches to overcome clock skew [52][53][54]. This implies that the presence of a global clock signal leads to more latency and power consumption.…”

Section: Introductionmentioning

confidence: 99%

“…Several successful industrial experiments have also been performed to support the asynchronous circuit design such as Intel RAPPID [68], IBM FIR filter [69,70], optimizing continuous-time digital signal processors [71,72], developing ultra-low-energy devices [73][74][75][76], system design to handle extreme temperature [77] and finally, developing alternative computing paradigms [78][79][80]; however, these experiments were not commercialized. One of the primary reasons for the absence of commercial asynchronous circuits is the absence of sufficiently mature asynchronous EDA tools [51,81]. Fortunately, several languages and design tools are being developed for asynchronous approach such as UNCLE (Unified NULL Convention Logic Environment) [82], Tangram [65,[83][84][85][86][87][88], CHP (communicating hardware processes) [89][90][91][92][93][94][95], BALSA [96], asynchronous circuit compiler [97][98][99][100], Petrify [101][102][103] and various other tools [104][105][106][107]…”

Section: Introductionmentioning

confidence: 99%

Asynchronous Floating-Point Adders and Communication Protocols: A Survey

2020

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Addition is the key operation in digital systems, and floating-point adder (FPA) is frequently used for real number addition because floating-point representation provides a large dynamic range. Most of the existing FPA designs are synchronous and their activities are coordinated by clock signal(s). However, technology scaling has imposed several challenges like clock skew, clock distribution, etc., on synchronous design due to presence of clock signal(s). Asynchronous design is an alternate approach to eliminate these challenges imposed by the clock, as it replaces the global clock with handshaking signals and utilizes a communication protocol to indicate the completion of activities. Bundled data and dual-rail coding are the most common communication protocols used in asynchronous design. All existing asynchronous floating-point adder (AFPA) designs utilize dual-rail coding for completion detection, as it allows the circuit to acknowledge as soon as the computation is done; while bundled data and synchronous designs utilizing single-rail encoding will have to wait for the worst-case delay irrespective of the actual completion time. This paper reviews all the existing AFPA designs and examines the effects of the selected communication protocol on its performance. It also discusses the probable outcome of AFPA designed using protocols other than dual-rail coding.

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Design of a clockless MSP430 core using mixed asynchronous design flow

Cited by 4 publications

References 16 publications

Snake: An asynchronous pipeline for ultra-low-power applications

Snake: An asynchronous pipeline for ultra-low-power applications

Implementation of an Asynchronous Micro-controlleron the Commercial FPGA

Asynchronous Floating-Point Adders and Communication Protocols: A Survey

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