Snake: An asynchronous pipeline for ultra-low-power applications

Abstract

Voltage scaling is an effective technique for ultra-low-power applications. However, PVT variation degrades the robust of traditional synchronous pipelines severely when voltage scales into the sub-threshold region. In this paper, we propose a register-based bundled-data asynchronous pipeline that can operate robustly in sub-threshold, called Snake. By looping the match delay line, the Snake halves the design overhead compared to other asynchronous pipelines. We also propose a practical asynchronous design methodology which is compatible with commercial EDA and needs only a few modifications to synchronous design flow.Monte-Carlo SPICE simulation shows that the pipelined multiplier applying the proposed techniques operates stably in 0.2 V and achieves minimum power 1.3 nW in 0.2 V, minimum energy 1.07 pJ per cycle in 0.3 V. It provides 6.7 times superiority over synchronous baseline design with 22% area overhead. Comparison with other works in the state of art shows the proposed techniques are quite competitive.

An enhanced reconfigurable dual-clock FIFO for inter-IP data transmission

“…In [20], synchronizers and one-hot coding are used to implement mixed-clock domain FIFOs, enabling communication between synchronous or asynchronous chips. It is worth noting that in [21] , although the asynchronous protocol demonstrates resilience to PVT variations, the latency associated with the handshake could adversely impact overall system performance. Asynchronous protocols could be further categorized into two types: two-phase and four-phase bundleddata protocols [22], with the bundled-data circuit representing the most cost-effective design option.In contrast, [23] highlighted that asynchronous FIFOs required more control logic than synchronous FIFOs, as their signal processing was not reliant on clock signals.…”