Design of a Fully Integrated Two-Stage Watt-Level Power Amplifier Using 28-nm CMOS Technology

Osmann, P.; Fuhrmann, Jorg; Dufrene, Krzysztof; Fritzin, Jonas; Moreira, Jose; Pretl, Harald; Springer, Andreas

doi:10.1109/tmtt.2015.2503343

Cited by 11 publications

(3 citation statements)

References 26 publications

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“…Stacked-FET High-Power Amplifiers transistors are stacked in order to increase the total breakdown voltage. Stacked transistor amplifiers are demonstrated in Si-based [4]- [11] technologies, GaAs [1], [12]- [18], and GaN [19] technologies.…”

Section: Design Procedures For Integrated Microwave Gaasmentioning

confidence: 99%

“…7, the parasitic gate capacitance C pg is parallel to the external gate admittance Y gX,n . This means that the effect of C pg can be taken into account by decreasing the obtained Y gX,n from (11) with a value Y pg . The external gate capacitance is equal to the required capacitance applied to the intrinsic transistor minus the parasitic gate capacitance…”

Section: Parasitic Capacitancesmentioning

confidence: 99%

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Design Procedure for Integrated Microwave GaAs Stacked-FET High-Power Amplifiers

Bent¹,

Hek²,

Vliet³

2019

IEEE Trans. Microwave Theory Techn.

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The application of stacked-FETs in power amplifiers allows for a supply voltage higher than supported by the breakdown voltage of a single transistor. Potential benefits of the increased supply voltage are reduced supply currents and a lower matching ratio at the output of the amplifier. Furthermore, an increased output power per chip area is obtained due to the reduction in passive structures resulting in more area-efficient power combining. In this paper, the procedure for the design of integrated microwave stacked-FET is discussed. Several options for the correct distribution of RF voltage and current swings are investigated and the relationship between the number of stacked transistors and bandwidth is addressed. The procedure is demonstrated by the design of an S-band GaAs stacked-FET containing three transistors. This stacked-FET is applied in an S-band HPA that has a PAE of more than 40% at an output power of 20 W, which is more than twice the output power of any previously reported GaAs stacked-FET HPA.

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Section: Design Procedures For Integrated Microwave Gaasmentioning

confidence: 99%

Section: Parasitic Capacitancesmentioning

confidence: 99%

Design Procedure for Integrated Microwave GaAs Stacked-FET High-Power Amplifiers

Bent¹,

Hek²,

Vliet³

2019

IEEE Trans. Microwave Theory Techn.

View full text Add to dashboard Cite

show abstract

“…In the literature, stacked PAs are largely exploited in CMOS technology [11][12][13][14][15][16][17][18], where the breakdown voltage is a major limit, but some examples can also be found in GaAs [19][20][21][22][23][24][25][26][27] and very few in GaN [28][29][30][31]. A main advantage of the stacked PA is that it can be profitably adopted as a basic high-power and high-gain cell to be further exploited in more complex PA architectures, from classical parallel combined PAs [32] to advanced architectures such as distributed PAs [33], spatially-combined PAs [34] and Doherty PAs [30,35].…”

Section: Introductionmentioning

confidence: 99%

Space-Compliant Design of a Millimeter-Wave GaN-on-Si Stacked Power Amplifier Cell through Electro-Magnetic and Thermal Simulations

et al. 2021

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The stacked power amplifier is a widely adopted solution in CMOS technology to overcome breakdown limits. Its application to compound semiconductor technology is instead rather limited especially at very high frequency, where device parasitic reactances make the design extremely challenging, and in gallium nitride technology, which already offers high breakdown voltages. Indeed, the stacked topology can also be advantageous in such scenarios as it can enhance gain and chip compactness. Moreover, the higher supply voltages and lower supply currents beneficially impact on reliability, thus making the stacked configuration an attractive solution for space applications. This paper details the design of two stacked cells, differing in their inter-stage matching strategy, conceived for space applications at Ka-band in 100 nm GaN-on-Si technology. In particular, the design challenges related to the thermal constraints posed by space reliability and to the electro-magnetic cross-talk issues that may arise at millimeter-wave frequencies are discussed. The best cell achieves at saturation, in simulation, 3 W of output power at 36 GHz with associated gain and efficiency in excess of 7 dB and 35%, respectively.

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Design of low power RF CMOS power amplifier structure with an optimal linear gain controller for future wireless communication

ArjunaraoVatti

Kumar

Haripriya

et al. 2021

J Ambient Intell Human Comput

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Design of a Fully Integrated Two-Stage Watt-Level Power Amplifier Using 28-nm CMOS Technology

Cited by 11 publications

References 26 publications

Design Procedure for Integrated Microwave GaAs Stacked-FET High-Power Amplifiers

Design Procedure for Integrated Microwave GaAs Stacked-FET High-Power Amplifiers

Space-Compliant Design of a Millimeter-Wave GaN-on-Si Stacked Power Amplifier Cell through Electro-Magnetic and Thermal Simulations

Design of low power RF CMOS power amplifier structure with an optimal linear gain controller for future wireless communication

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