Design of a Host Interface Logic for GC-Free SSDs

Choi, Won-Il; Kwon, Miryeong; Srikantaiah, Shekhar; Yoo, Joonhyuk; Kandemir, Mahmut

doi:10.1109/tcad.2019.2919035

Cited by 11 publications

(6 citation statements)

References 38 publications

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“…There are several reasons, but the greatest weakness of ISP ironically is that it needs to process data where data is stored, i.e., at the flash device. Flash cannot be directly used as block storage because of its low-level characteristics, such as I/O operation asymmetry and low reliability [10,37,38,55,56,78]. Thus, flash requires tight integration with multiple firmware and controller modules [98,99], which renders ISP difficult to be implemented within an SSD.…”

Section: Storage As a Gnn Acceleratormentioning

confidence: 99%

Hardware/Software Co-Programmable Framework for Computational SSDs to Accelerate Deep Learning Service on Large-Scale Graphs

Kwon¹,

Gouk²,

Lee³

2022

Preprint

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Graph neural networks (GNNs) process large-scale graphs consisting of a hundred billion edges. In contrast to traditional deep learning, unique behaviors of the emerging GNNs are engaged with a large set of graphs and embedding data on storage, which exhibits complex and irregular preprocessing.We propose a novel deep learning framework on large graphs, HolisticGNN, that provides an easy-to-use, nearstorage inference infrastructure for fast, energy-efficient GNN processing. To achieve the best end-to-end latency and high energy efficiency, HolisticGNN allows users to implement various GNN algorithms and directly executes them where the actual data exist in a holistic manner. It also enables RPC over PCIe such that the users can simply program GNNs through a graph semantic library without any knowledge of the underlying hardware or storage configurations.We fabricate HolisticGNN's hardware RTL and implement its software on an FPGA-based computational SSD (CSSD). Our empirical evaluations show that the inference time of HolisticGNN outperforms GNN inference services using high-performance modern GPUs by 7.1× while reducing energy consumption by 33.2×, on average.

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Section: Storage As a Gnn Acceleratormentioning

confidence: 99%

Hardware/Software Co-Programmable Framework for Computational SSDs to Accelerate Deep Learning Service on Large-Scale Graphs

Kwon¹,

Gouk²,

Lee³

2022

Preprint

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Section: Related Workmentioning

confidence: 99%

“…Garbage collection and resource contention on I/O buses (channels) of SSDs will block all incoming read/write requests to the same I/O buses, which must bring about greater turnaround time for these requests [10]. To be specific, the first two partial operations of GC (i.e., Read and Write) block the whole channel, and the last partial operation of Erase exclusively occupies the target chip [4,10]. To minimize the negative effects on I/O latency caused by garbage collection, it is expected to either complete GC operations within less time [7,23,25] or place a higher priority to blocked I/O requests [1,14,26] or perform GC operations in the idle time intervals [4,9,11,16].…”

Section: Related Workmentioning

confidence: 99%

“…Let U all representing the total pages of cache for holding valid pages in GC, and U θ is the available pages of cache before processing I/O requests in the time slot of θ . Therefore, we can obtain the constraint on cache use for correctly performing Read or Write operations in the time slot of θ , as illustrated in Equation (10).…”

Section: Assembling and Scheduling Partial Gcmentioning

confidence: 99%

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Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs

Sha

Song

et al. 2021

ACM Trans. Archit. Code Optim.

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This article proposes a low I/O intensity-aware scheduling scheme on garbage collection (GC) in SSDs for minimizing the I/O long-tail latency to ensure I/O responsiveness. The basic idea is to assemble partial GC operations by referring to several determinable factors (e.g., I/O characteristics) and dispatch them to be processed together in idle time slots of I/O processing. To this end, it first makes use of Fourier transform to explore the time slots having relative sparse I/O requests for conducting time-consuming GC operations, as the number of affected I/O requests can be limited. After that, it constructs a mathematical model to further figure out the types and quantities of partial GC operations, which are supposed to be dealt with in the explored idle time slots, by taking the factors of I/O intensity, read/write ratio, and the SSD use state into consideration. Through a series of simulation experiments based on several realistic disk traces, we illustrate that the proposed GC scheduling mechanism can noticeably reduce the long-tail latency by between 5.5% and 232.3% at the 99.99th percentile, in contrast to state-of-the-art methods.

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“…This makes the power of internal DRAM buffers and controllers dominant for the I/O services rather than the power of backend flash. One of the performance bottlenecks that most SSDs suffer from is garbage collections [21,35,37,39,64]. Since flash does not allow to overwrite data without erasing a flash block, flash firmware [40,50,51] forwards all incoming overwrite requests to a new space (i.e., block), which was erased in a previous stage, and remaps the target addresses, associated with the request, to the new block.…”

Section: Is the Traditional Nvme Multi-queue Mechanism Also Affordabl...mentioning

confidence: 99%

Faster than Flash: An In-Depth Study of System Challenges for Emerging Ultra-Low Latency SSDs

Koh

Jang

Lee

et al. 2019

2019 IEEE International Symposium on Workload Characterization (IISWC)

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Emerging storage systems with new flash exhibit ultra-low latency (ULL) that can address performance disparities between DRAM and conventional solid state drives (SSDs) in the memory hierarchy. Considering the advanced low-latency characteristics, different types of I/O completion methods (polling/hybrid) and storage stack architecture (SPDK) are proposed. While these new techniques are expected to take costly software interventions off the critical path in ULL-applied systems, unfortunately no study exists to quantitatively analyze system-level characteristics and challenges of combining such newly-introduced techniques with real ULL SSDs.In this work, we comprehensively perform empirical evaluations with 800GB ULL SSD prototypes and characterize ULL behaviors by considering a wide range of I/O path parameters, such as different queues and access patterns. We then analyze the efficiencies and challenges of the polled-mode and hybrid polling I/O completion methods (added into Linux kernels 4.4 and 4.10, respectively) and compare them with the efficiencies of a conventional interrupt-based I/O path. In addition, we revisit the common expectations of SPDK by examining all the system resources and parameters. Finally, we demonstrate the challenges of ULL SSDs in a real SPDK-enabled server-client system. Based on the performance behaviors that this study uncovers, we also discuss several system implications, which are required to take a full advantage of ULL SSD in the future.

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Design of a Host Interface Logic for GC-Free SSDs

Cited by 11 publications

References 38 publications

Hardware/Software Co-Programmable Framework for Computational SSDs to Accelerate Deep Learning Service on Large-Scale Graphs

Hardware/Software Co-Programmable Framework for Computational SSDs to Accelerate Deep Learning Service on Large-Scale Graphs

Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs

Faster than Flash: An In-Depth Study of System Challenges for Emerging Ultra-Low Latency SSDs

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