Design of Adiabatic Logic Based Comparator for Low Power and High Speed Applications

Samuel, T. S. Arun; Darwin, S.; Arumugam, Niveditha

doi:10.21917/ijme.2017.0064

Cited by 4 publications

(3 citation statements)

References 11 publications

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“…The term adiabatic is refers to thermodynamic process in which no energy is exchanged with the environment and hence no energy is lost in the form of energy consumption [31]. For energy usage in the adiabatic circuit, there are three rules [32], [33]: i)…”

Section: Preliminariesmentioning

confidence: 99%

D flip-flop design by adiabatic technique for low power applications

Sanadhya

Sharma²

2022

IJEECS

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Indigital circuits, energy reduction is the most important parameter in the design of handy and battery-operated devices. Flip- flop is an important component in any digital system. By improving the performance of flip-flop, complete system performance is better. This paper addresses the design of D flip-flop using direct current diode-based positive feedback adiabatic logic (DC-DB PFAL) at various frequencies at 45nm technology node. Further, the layout for the proposed design is also presented. The performance analysis is carried out for delay, power dissipation, power delay product and transistor count. Circuit simulation is done by using cadence virtuoso tool at 10 MHz and 100 MHz frequencies. The results show an improvement in power dissipation of 18% with less transistors count compared to exiting designs in the literature.

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Section: Preliminariesmentioning

confidence: 99%

D flip-flop design by adiabatic technique for low power applications

Sanadhya

Sharma²

2022

IJEECS

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“…In addition to this, the implementation of inverter-based low power adiabatic dynamic comparator has been proposed [18], where, back-toback inverter of a conventional dynamic comparator is being replaced by the Diode free adiabatic logic inverter that utilizes the adiabatic logic concept for power optimization. Various magnitude comparator designs have been reported in the literature [19][20][21]. Kaza et al has designed secured MPFAL logic for IoT applications.…”

Section: Introductionmentioning

confidence: 99%

Adiabatic Logic Based Energy Efficient Architecture of 1-Bit Magnitude Comparator for IOT Applications

Sanadhya¹,

Sanadhya²

2022

Journal of Internet Technology

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<p>The Internet of Things (IoT) applies the sensors and microcontrollers and links them through the internet. The eventual objective of low-power devices for Internet of Things is to lesser the overall system power and to extend battery life. For the development of energy efficient IoT devices, novel adiabatic techniques are proposed. By improving the performance of the comparator, one can improvise the whole system performance. The efficacy of computing devices depends on the performance of arithmetic circuits, including comparator. This paper proposes 1-bit comparator design using adiabatic techniques such as DC-DB PFAL (Direct current diode-based positive feedback adiabatic logic) and MPFAL (Modify positive feedback adiabatic logic) which are well-suited with an extensive range of applications (e.g. IoT sensors and an inbuilt analog to digital converter). For performance analysis, the results are compared together along with the other adiabatic and non adiabatic designs already reported in the literature. This paper proposes a way to decrease the dissipation of power and transistor count in binary circuits as it is one of the primary concerns. From the results, it is found that the design using DC-DB PFAL logic shows an improvement in power-delay-product of 69%, 94% and 90% compared to MPFAL, PFAL and ECRL techniques respectively.</p> <p> </p>

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“…A novel modified comparator is a combination of adiabatic logic 2N-2N2P and two static adiabatic clocked logic (2N-2N2P and PASCAL), efficient charge recovery logic adiabatic and two phases static adiabatic static clocked logic (ECRL and 2PASCL)(T. S. A. Samuel et al 2017). The offset is suppressed by dynamically storing the comparator offset on the input capacitors (Liu et al 2017).…”

Section: Introductionmentioning

confidence: 99%

Construction of pMos Logic based Low Power High Speed Comparator Compare with nMos Logic

Reddy¹,

Dass²

2021

alinteri

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Aim: The aim of this work is to construct an innovative pMos logic based comparator and analyze the power consumption and compare with the nMos logic based comparator. Material and methods: The comparator is designed by using the Tanner tool version 16.01 for simulation and verification. By varying the length of a transistors in a circuit the power values were obtained. This experiment is performed for 20 different values of length. Results: The power consumption of a pMos logic based comparator was minimum (2.2656 ± 0.37933), followed by the nMos logic based comparator (7.7494 ± 0.41603), the less power consumption seen in pMos logic based comparator significance (.955). Conclusion: The consumption of power by the constructed pMos logic based comparator appears to have less power consumption than the nMos logic based comparator.

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Design of Adiabatic Logic Based Comparator for Low Power and High Speed Applications

Cited by 4 publications

References 11 publications

D flip-flop design by adiabatic technique for low power applications

D flip-flop design by adiabatic technique for low power applications

Adiabatic Logic Based Energy Efficient Architecture of 1-Bit Magnitude Comparator for IOT Applications

Construction of pMos Logic based Low Power High Speed Comparator Compare with nMos Logic

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