Design of an optimal test pattern generator for built-in self testing of path delay faults

Abstract

A novel design of a test pattern generator (TPG) for built-in self-testing (BIST) of path delay faults, is proposed. For a n n-input CUT, the TPG generates a sequence of length (n.2" +1), that includes all n.2" single-input-change (SIC) test pairs, and hence optimal. The generation of such a sequence of minimum length (i.e., n.2' + 1 ) was a n open problem. A simple iterative circuit of the TPG is then constructed. This provides minimum test application time for testing path delay faults, and compares favorably with the earlier BIST designs.

Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time

“…However, the hardware overhead of [37] is rather high, thus the value of the scheme lies mainly on its high theoretical significance. The hardware overhead of the scheme is, according to [37], flip-flops, XOR gates (2-input), OR gates (2-input), AND gates (2-input) and 1 NOT gate.…”

“…The hardware overhead of the technique is flip-flops and 2-input XOR gates. In [37], Das et al presented an optimal solution to the problem of generating SIC pairs, in the sense that the pairs are generated within time equal to the theoretical minimum, i.e., . However, the hardware overhead of [37] is rather high, thus the value of the scheme lies mainly on its high theoretical significance.…”

“…In [37], Das et al presented an optimal solution to the problem of generating SIC pairs, in the sense that the pairs are generated within time equal to the theoretical minimum, i.e., . However, the hardware overhead of [37] is rather high, thus the value of the scheme lies mainly on its high theoretical significance. The hardware overhead of the scheme is, according to [37], flip-flops, XOR gates (2-input), OR gates (2-input), AND gates (2-input) and 1 NOT gate.…”

“…In this section, ARN will be compared with the techniques proposed hitherto [5]- [8], [10] and [37], in terms of hardware overhead and time required to generate the entire sequence of SIC pairs.…”

“…For the comparisons, we shall assume that (a) an -stage register (consisting of flip-flops) exists at the inputs of the -input CUTfor the case of [5]- [7], [10], [37] and we shall calculate the overhead imposed on these flip-flops. For the case of ARN, as well as for the case of [8], we shall assume the existence of the accumulator whose inputs are driven by a barrel shifter.…”