Design of CMOS CML circuits for high-speed broadband communications

Green, M.M.; Singh, Ullas

doi:10.1109/iscas.2003.1205937

Cited by 28 publications

(17 citation statements)

References 3 publications

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“…To achieve faster logic operation and maintain DC gain with less parasitics, it is beneficial to maximize the current density of differential pair devices according to [4]. Choosing a swing level was based on the two facts.…”

Section: Comparison and Simulation Resultsmentioning

confidence: 99%

A 20GHz variability-aware robust, high-speed and low-power MOS CML latch

Lee

2012

IEICE Electron. Express

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Abstract:In a deep submicron CMOS process, variability puts a strict requirement on noise margin in MOS current-mode logic (MCML) gates. A usual approach to achieve noise margin is to increase DC gain by sizing up differential pairs. However this results in slow output settling, which limits the maximum operating speed. Thus we propose a novel MCML latch to mitigate this trade-off by using alternating low and high gain buffer structure on a bandwidth limited node. The proposed MCML latch is designed to operate at 20 GHz clock in a 32 nm CMOS process and is compared with a conventional MCML latch to prove its superiority in terms of speed, power and reliability especially when bandwidth is limited.

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Section: Comparison and Simulation Resultsmentioning

confidence: 99%

A 20GHz variability-aware robust, high-speed and low-power MOS CML latch

Lee

2012

IEICE Electron. Express

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“…Also, static CMOS inverters are sensitive to and cause significant power rail bounce. It is perhaps good to note that this is also a source of jitter [48].…”

Section: Recommendations For a Large Bandwidth Amplifiermentioning

confidence: 99%

A Jittered-Sampling Correction Technique for ADCs

Tourabaly

Osseiran

2008

4th IEEE International Symposium on Electronic Design, Test and Applications (Delta 2008)

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“…For a 1.8 V supply, typical CML voltage levels are between 400 mV and 800 mV. At multi-Gb/sec data rates, CML circuits achieve much faster speeds than static CMOS logic gates [3]. …”

Section: Analog Decision-feedback Equalizer Designmentioning

confidence: 99%

A 10-Gb/sec unclocked current-mode logic (CML) analog decision-feedback equalizer (ADFE) in 0.18-μm CMOS

Chandramouli

Bien

Kim

et al. 2007

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference

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An unclocked analog decision-feedback equalizer (ADFE) is implemented in a 0.18-µm 40 GHz f t CMOS process to equalize legacy FR-4 backplane channels at 8~10-Gb/sec. The critical first feedback-loop latency requirement of the DFE is met by using a novel unclocked feedback topology and currentmode logic (CML) circuit building blocks. The circuit consists of a 4-tap linear analog feed-forward filter that cancels pre-cursor inter-symbol interference (ISI) to partially open the eye and a novel 1-tap analog tunable CML feedback filter that enables cancellation of the first post-cursor at 10-Gb/sec without the use of smaller process nodes or speculative techniques. The chip with pads occupies 1.04 mm 2 and draws 240 mA DC current from a 1.8 V supply at a typical process corner. The ADFE is used to equalize 20 inches of FR-4 backplane traces at 8-Gb/sec and 10-Gb/sec.

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Design of CMOS CML circuits for high-speed broadband communications

Cited by 28 publications

References 3 publications

A 20GHz variability-aware robust, high-speed and low-power MOS CML latch

A 20GHz variability-aware robust, high-speed and low-power MOS CML latch

A Jittered-Sampling Correction Technique for ADCs

A 10-Gb/sec unclocked current-mode logic (CML) analog decision-feedback equalizer (ADFE) in 0.18-μm CMOS

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Design of CMOS CML circuits for high-speed broadband communications

Cited by 28 publications

References 3 publications

A 20GHz variability-aware robust, high-speed and low-power MOS CML latch

A 20GHz variability-aware robust, high-speed and low-power MOS CML latch

A Jittered-Sampling Correction Technique for ADCs

A 10-Gb/sec unclocked current-mode logic (CML) analog decision-feedback equalizer (ADFE) in 0.18-&#x03BC;m CMOS

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A 10-Gb/sec unclocked current-mode logic (CML) analog decision-feedback equalizer (ADFE) in 0.18-μm CMOS