2013 2nd International Conference on Advances in Electrical Engineering (ICAEE) 2013
DOI: 10.1109/icaee.2013.6750359
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Design of low power pulsed flip-flop using sleep transistor scheme

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Cited by 3 publications
(3 citation statements)
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“…Therefore, an efficient FF design may significantly enhance the circuit power consumption. In literature, various circuits of D-FFs are proposed and investigated for low power application, each of which has its own pros and cons [18][19][20][21][22]. For comparison purposes, a performance analysis is carried out on several FF designs and presented in Tables 2-4.…”
Section: Flip-flop Cmos Designmentioning
confidence: 99%
See 1 more Smart Citation
“…Therefore, an efficient FF design may significantly enhance the circuit power consumption. In literature, various circuits of D-FFs are proposed and investigated for low power application, each of which has its own pros and cons [18][19][20][21][22]. For comparison purposes, a performance analysis is carried out on several FF designs and presented in Tables 2-4.…”
Section: Flip-flop Cmos Designmentioning
confidence: 99%
“…Optimal D-FF designs must achieve a trade-off between the power consumption, the number of transistors (circuit size) and the perfor- [22] Failed Failed 104 150 TSPC [18] Failed at the required frequency CPEPTFF [22] Failed at the required frequency mance (delay) at ultra-low voltage supply. Therefore, the power delay product (PDP) based metric is used for comparative analysis and in particular for low power systems.…”
Section: Flip-flop Cmos Designmentioning
confidence: 99%
“…In literature, various circuits of D-FFs are proposed and investigated for low power application, each of which has its own pros and cons [9], [10], [11], [12]. Optimal D-FF designs must achieve a trade-off between the number of transistors (circuit size) and the functionality at ultra low voltage supply.…”
Section: A Flip-flop Cmos Designmentioning
confidence: 99%