In this paper, a novel low power 20T alternative adder cell featuring modified swing restored complementary pass transistor logic (SR-CPL) is proposed. This alternative adder cell structure performs better in terms of power dissipation, propagation delay and power-delay-product (PDP) when compared with 26T SR-CPL and other adder cells implemented using conventional logic styles. As compared with 26T SRCPL adder cell, the proposed adder cell reduces power by 23.15%, delay by 6.15% and PDP by 27.91%. This design is carried-out using a TSMC 45nm CMOS technology in Cadence Virtuoso Analog Design Environment at 45nm technology and simulated using Spectre simulator. This adder cell can be used as a computation element in various DSP architectures and microprocessors resulting in high performance.

No abstract

No abstract

No abstract

No abstract