Design of multiple-metal stacked inductors incorporating an extended physical model

Abstract

Modern analog circuits are heavily dependent on inductor performance, where the poor inductor quality factor ( ) of silicon processes leads to degradation in circuit efficacy, especially at RF and microwave frequencies. Several techniques have been proposed to enhance the of integrated on-chip inductors, but the most effective method of improvement is to lower the series resistance by increasing the inductor metal thickness. This paper presents the most cost-effective method of achieving a thick metal by using a standard 0.18-m multilayer BiCMOS process. An expanded physically based model for multiple-metal stacked inductors is presented, which expands on previous research to show the effects and limitations of stacking two, three, and four metal layers in a five-metal-layer process. The excellent accuracy of this geometrical model is illustrated with respect to a range of inductor designs showing that an improvement in of more than 50% may be achieved. Due to the increased parasitics in multilayer structures, the improvement is very frequency dependent, which is clearly predicted with the expanded model. The predictive capability of the model is further used to provide detailed insight into the effectiveness of a patterned ground shield for different substrate characteristics. This predictive ability will contribute greatly to first time right inductor designs and eliminate the expensive and time-consuming fabrication iterations required to fine tune other inductor models.Index Terms-Integrated stacked inductor model, patterned ground shield (PGS), improvement, prediction.

Microwave modeling and parameter extraction method for multilayer on-chip inductors

“…In order to overcome the limitations of previous literature, we have developed a new equivalent circuit model for 3D multilayer on-chip inductors, and a semi-analytical method for extracting the model parameters is investigated. In contrast with previous publications [14][15][16], this method has the advantages as This paper is organized as follows. Section II gives the proposed equivalent-circuit model of 3D multilayer onchip inductors, and then discusses the basic procedure for extracting the model parameters.…”

Minimization of Via Count in Multiple-Metal Inductors: Performance Characterization and Physical Modelling

“…The calculation of the other parameters remains the same [8], with the fringe and coupling capacitance being modelled similar to interconnect capacitance using an effective permittivity for the process stack [9]. Each element of the top-level model as presented in Fig.…”

“…Each element of the top-level model as presented in Fig. 1 is calculated from first principles [8]. Fig.…”

“…The model for multiple-metal layer inductors using the maximum number of vias has been presented before [8], and the adjustment of this model to account for fewer vias forms part of the focus of this paper. Section II shows the top level model which is valid regardless of the inductor topology.…”

PSO-based evolutionary optimization for black-box modeling of arbitrary shaped on-chip RF inductors

“…This inaccuracy comes from the approximations made during analytical modeling of the complex field coupling. In spite of this limitation, recent publications show fairly accurate physical models of planer inductors [4] even for stack inductors [5]. But these physical models are valid only for a class of geometry.…”