Design of Transform and Quantization Circuit for Multi-Standard Integrated Video Decoder

Abstract

Transfer Level) and synthesized into a gate-level circuit using 130nm standard cell library. The resultant circuit This paper presents a new method to design the circuit that includes 69,928 logic gates and its maximum operating can perform the inverse transform and inverse quantization frequency is 123.1MHz. operations for three popular video compression standards WMV9, MPEG-4 and H.264. We introduced a delta 2. BACKGROUND coefficient matrix and implemented the integrated inverse transform circuit based on the proposed idea. We designed The IDCT of WMV9 is defined as the following matrix the integrated inverse quantization circuit using a shared equations: multiplier. The entire circuit was verified on the SoC platform board, synthesized into a gate-level circuit using EMXN= (XMXN WNXN+ 4) >>3 130nm standard cell library and showed its efficiency in RmN (WT £m+ C 1 1-4244-1222-6/07/$25.00 ©)2007 IEEE

Efficient inverse transform architectures for multi-standard video coding applications

“…Table 2 shows a comparison of the proposed and existing VC-1 1-D 8-point inverse transforms without rounding units. Lee and Cho [21] proposed a design for multi-standard transforms. The architecture for the VC-1 1-D 8-point inverse transform requires 5529 gates, with a throughput of 2 pixels/cycle.…”

“…This design achieves high throughput but requires many logic gates. Lee and Cho [21,22] suggested a transform architecture for supporting JPEG, MPEG-4, VC-1 and H.264/AVC decoders that uses adders and shifters instead of multipliers. However, the architecture for H.264/AVC supports only the baseline, main and extended profiles, so only 4-point inverse transforms are used.…”

An efficient architecture of multiple 8×8 transforms for H.264/AVC and VC-1 decoders

“…H.264/AVC and VC-l both provide 8-point integer transforms to attain higher compression ratio. [5], [6] carried out transform architecture for video decoder supporting JPEG, MPEG-4, VC-l and H.264/AVC by using adders and shifters instead of multipliers. However, the architecture for H.264/AVC only supports the baseline, main, and extended profiles, so only 4-point inverse transforms are designed instead of 8-point inverse transform.…”

Efficient Low-Cost Sharing Design of Fast 1-D Inverse Integer Transform Algorithms for H.264/AVC and VC-1

“…In [5], the fast algorithm for VC-1 is developed and the computational complexities can be reduced efficiently. In [6] and [7], the authors analyze the three transforms and quantization operations in detail to find the sharing adders and multipliers. The rest of this letter is organized as follows.…”

“…By applying the symmetric property, the transform matrix in (2) can be rewritten as follows: (5) where and Then the computational complexities of are eight additions. By permuting the columns of , can be rewritten as follows: (6) where and . By using the direct sum operator, the matrix is expressed as the form of the diagonal matrix.…”