Design optimizations to improve placeability of partial reconfiguration modules

Abstract

Abstract-In partially reconfigurable architectures, system components can be dynamically loaded and unloaded allowing resources to be shared over time. This paper focuses on the relation between the design options of partial reconfiguration modules and their placement at run-time. For a set of dynamic system components, we propose a design method that optimizes the feasible positions of the resulting partial reconfiguration modules to minimize position overlaps. We introduce the concept of subregions, which guarantees the parallel execution of a certain number of partial reconfiguration modules for tiled reconfigurable systems. Experimental results, which are based on a Xilinx Virtex-4 implementation, show that at run-time the average number of available positions can be increased up to 6.4 times and the number of placement violations can be reduced up to 60.6%.

A Roadmap for Autonomous Fault-Tolerant Systems

“…They could allocate a module in a target position where there were different types of resources from the region for which it was synthesized. Finally, in [34] the authors describe a design method for selecting a synthesis region for the relocatable modules with the objective of optimizing the placement at runtime. By using herein presented state-of-the-art trends, system flexibility is significantly enhanced when compared with traditionally used Difference based and Module based DPR design flows [35], which lead to only rigid slot-based TL1 systems.…”

Applying dynamic reconfiguration in the mobile robotics domain

“…The partitioning depends on the properties of the selected device, on the application requirements, and on the selected placement approach. The homogeneous communication infrastructure that is generated in the INDRA flow enables Partially Reconfigurable modules (PR modules) to be placed at any position providing sufficient resources [Koester et al 2009]. In this article, a quite simple scheme is used: the FPGA is divided into two parts, namely a static region utilizing 20% of the FPGA resources (slices) and a dynamically reconfigurable region, comprising 80% of the available FPGA slices.…”

Design Optimizations for Tiled Partially Reconfigurable Systems

“…Using the overlap graph the computation of the position weights is done in two steps. First, the probability weights (2) are computed for each vertex , where denotes the probability of an allocation of the PR module . The probability weight indicates the probability of a feasible position to be chosen, if all tiles in the PR region are available and a random placement is applied.…”

“…The proposed communication infrastructure enables the placement of PR modules in a tiled partially reconfigurable system and avoids restricting the number of feasible positions of the PR modules. As suggested in [2], the placeability of a PR module can be further enhanced at design-time by optimizing the area the PR module is initially synthesized for. This area is referred to as synthesis region.…”

“…• The design-time optimization presented in [2] uses exhaustive search and is therefore only suitable for small problem sizes. For a larger set of PR modules, a heuristic approach is presented, which is based on a genetic algorithm.…”