Design review and innovations in low-voltage differential signaling drivers

Rivera, Aixa; Bravo, Edna Negron de; Jiménèz, Manuel; Palomera, Rogelio

doi:10.1109/mwscas.2004.1354364

Cited by 4 publications

(2 citation statements)

References 3 publications

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“…In spite of the low transconductance, large parasitic element and limited cut-off frequency of CMOS, LVDS interface designs with high performance in standard CMOS process were reported in Refs. [3][4][5][6][7][8][9], but further increase in bandwidth and reduction in power and die area are desired for high data transmission rate and I/O density.…”

Section: Introductionmentioning

confidence: 99%

Low-power LVDS I/O interface for above 2Gb/s-per-pin operation

Wang

You-bao

2009

J. Electron.(China)

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Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three amplifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power consumption of 13.2 mW and 8.3 mW respectively.

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Section: Introductionmentioning

confidence: 99%

Low-power LVDS I/O interface for above 2Gb/s-per-pin operation

Wang

You-bao

2009

J. Electron.(China)

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“…Most of them, however, require accurate current biasing. To generate such current, a band-gap reference and an external resistor is mostly used [3,6,8,9]. Some proposed solutions do not describe biasing circuit [4,7].…”

Section: General Informationmentioning

confidence: 99%