DESTINY: A Tool for Modeling Emerging 3D NVM and eDRAM caches

Poremba, Matt; Mittal, Sparsh; Liu, Dong; Vetter, Jeffrey S.; Xie, Yuan

doi:10.7873/date.2015.0733

Cited by 105 publications

(61 citation statements)

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“…We modelled the area and power for the main accelerator SRAM bu↵ers, NBin and NBout using CACTI v5.3 [28]. The eDRAM energy was modelled with Destiny [30]. Table 4 reports the modelled characteristics of these memory elements.…”

Section: Methodsmentioning

confidence: 99%

Proteus

Judd

Albericio

Hetherington

et al. 2016

Proceedings of the 2016 International Conference on Supercomputing

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This work exploits the tolerance of Deep Neural Networks (DNNs) to reduced precision numerical representations and specifically, their recently demonstrated ability to tolerate representations of di↵erent precision per layer while maintaining accuracy. This flexibility enables improvements over conventional DNN implementations that use a single, uniform representation. This work proposes Proteus, which reduces the data tra c and storage footprint needed by DNNs, resulting in reduced energy and improved area efficiency for DNN implementations. Proteus uses a di↵er-ent representation per layer for both the data (neurons) and the weights (synapses) processed by DNNs. Proteus is a layered extension over existing DNN implementations that converts between the numerical representation used by the DNN execution engines and the shorter, layer-specific fixedpoint representation used when reading and writing data values to memory be it on-chip bu↵ers or o↵-chip memory.Proteus uses a novel memory layout for DNN data, enabling a simple, low-cost and low-energy conversion unit.We evaluate Proteus as an extension to a state-of-the-art accelerator [7] which uses a uniform 16-bit fixed-point representation. On five popular DNNs Proteus reduces data tra c among layers by 43% on average while maintaining accuracy within 1% even when compared to a single precision floating-point implementation. As a result, Proteus improves energy by 15% with no performance loss. Proteus also reduces the data footprint by at least 38% and hence the amount of on-chip bu↵ering needed resulting in an implementation that requires 20% less area overall. This area savings can be used to improve cost by building smaller chips, to process larger DNNs for the same on-chip area, or to incorporate an additional three execution engines increasing peak performance bandwidth by 18%.

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Section: Methodsmentioning

confidence: 99%

Proteus

Judd

Albericio

Hetherington

et al. 2016

Proceedings of the 2016 International Conference on Supercomputing

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“…3D stacking technology enables modular integration of STT-RAM caches with minimal impact on processor design [114]. They evaluate several configurations where different levels of cache hierarchy are implemented in SRAM, STT-RAM etc.…”

Section: Techniques Related To Nvmsmentioning

confidence: 99%

“…They show that the outer-dies can shield more than 90% particle strikes for the innerdies which leads to a heterogeneous error rate across layers in a 3D chip. 3D integration also provides opportunities of heterogeneous integration, since different layers can be designed using different technologies [114]. Using this feature, the outer layer can be designed using Silicon-On-Insulator (SOI) technology which is more resilient to particle strikes.…”

Section: Effect Of 3d On Reliabilitymentioning

confidence: 99%

A Survey of Techniques for Modeling and Improving Reliability of Computing Systems

Mittal

Vetter

2016

IEEE Trans. Parallel Distrib. Syst.

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Recent trends of aggressive technology scaling have greatly exacerbated the occurrences and impact of faults in computing systems. This has made 'reliability' a first-order design constraint. To address the challenges of reliability, several techniques have been proposed. This paper provides a survey of architectural techniques for improving resilience of computing systems. We especially focus on techniques proposed for microarchitectural components, such as processor registers, functional units, cache and main memory etc. In addition, we discuss techniques proposed for non-volatile memory (NVM), GPUs and 3D-stacked processors. To underscore the similarities and differences of the techniques, we classify them based on their key characteristics. We also review the metrics proposed to quantify vulnerability of processor structures. We believe that this survey will help researchers, system-architects and processor designers in gaining insights into the techniques for improving reliability of computing systems.

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“…The retention period of eDRAM varies exponentially with the temperature [28], and hence, DESTINY scales the retention period accordingly to model the effect of the temperature. DESTINY provides the refresh latency, energy and power as the output of the tool.…”

Section: Edram Modelmentioning

confidence: 99%

“…Typically, a charged capacitor represents a "1", while a discharged capacitor represents a "0". Over time, eDRAM loses charge, and hence, it requires periodic refresh operations [28].…”

Section: Data Storage Mechanism Of Memory Technologiesmentioning

confidence: 99%

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Mittal

Wang

Vetter

2017

JLPEA

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Abstract:To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparsh_mittal/destiny_v2.

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DESTINY: A Tool for Modeling Emerging 3D NVM and eDRAM caches

Cited by 105 publications

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Proteus

Proteus

A Survey of Techniques for Modeling and Improving Reliability of Computing Systems

DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

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