Detailed analysis of FIBL in MOS transistors with high-k gate dielectrics

Mohapatra, Nihar R.; Desai, Madhav P.; Rao, V. Ramgopal

doi:10.1109/icvd.2003.1183121

Cited by 13 publications

(4 citation statements)

References 13 publications

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“…However, these studies have not explained the physical mechanism of the FIBL effect thoroughly. Mohaoatra et al [11] proposed an equivalent electrical distance theory to describe the FIBL effect, but the influence of the spacer on the device characteristics has not been included.…”

Section: Introductionmentioning

confidence: 99%

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-kgate dielectrics

Ma¹,

Liu²,

Kuang³

et al. 2012

Chinese Phys. B

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The fringing-induced barrier lowering (FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator. An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect. The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance. Based on equivalent capacitance theory, the influences of channel length, junction depth, gate/lightly doped drain (LDD) overlap length, spacer material and spacer width on FIBL is thoroughly investigated. A stack gate dielectric is presented to suppress the FIBL effect.

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Section: Introductionmentioning

confidence: 99%

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-kgate dielectrics

Ma¹,

Liu²,

Kuang³

et al. 2012

Chinese Phys. B

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“…[5][6][7][8] Among the comprehensive studies for the high-κ=metal gate (HKMG), the lateral field penetration through the high-κ dielectric has been issued accompanying the fringing field induced barrier lowering (FIBL) effects such as degradation of threshold voltage (V th ), subthreshold swing (SS), and I off , which are quite different from the drain induced barrier lowering (DIBL) caused by the reverse bias on the channelto-drain junction. [9][10][11][12][13][14][15][16] In this work, however, we discovered that the amount of gate induced drain leakage (GIDL) suppression by a high-κ dielectric is sufficient to mitigate the FIBL effects at somehow optimal high-κ permittivity region. Since the GIDL current is proportionally dependent on the electric field intensity owing to the base on the band-to-band tunneling (BTBT) mechanism, it is possible to suppress the GIDL currents with a reduced electric field through the high-κ dielectrics.…”

Section: Introductionmentioning

confidence: 93%

Gate induced drain leakage reduction with analysis of gate fringing field effect on high-κ/metal gate CMOS technology

Jang

Shin

Jung

et al. 2015

Jpn. J. Appl. Phys.

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We suggest the optimum permittivity for a high-κ/metal gate (HKMG) CMOS structure based on the trade-off characteristics between the fringing field induced barrier lowering (FIBL) and gate induced drain leakage (GIDL). By adopting the high-κ gate dielectric, the GIDL from the band-to-band tunneling at the interface of gate and lightly doped drain (LDD) is suppressed with wide tunneling width owing to the enhanced fringing field, while the FIBL effects is degenerated as the previous reports. These two effects from the gate fringing field are studied extensively to manage the leakage current of HKMG for low power applications.

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“…Ref. [20] reports the characteristics of the LAC device with high-gate dielectric. It was noted that the strong coupling of source to the drain via the high-gate insulator is only slightly affected by channel engineering.…”

Section: Discussionmentioning

confidence: 99%

SEU reliability analysis of advanced deep-submicron transistors

Jain

Vasi

Lal

2005

IEEE Trans. Device Mater. Relib.

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Abstract-A systematic evaluation of the single-event-upset (SEU) reliability of the advanced technologies-high-gate dielectric, elevated source-drain (E-SD), and lateral asymmetric channel (LAC) MOSFETs is presented for the first time in this work. Our simulations results gives a clear view of how the short channel effects in a device governs its SEU reliability and how this reasoning evolves at the circuit level. It is shown that devices with worsened short-channel effects (high-gate dielectric transistors) have a significantly reduced SEU-reliability in contrast to the devices with controlled short-channel effects (LAC and E-SD) or even a conventional device.Index Terms-charge enhancement, elevated source-drain, high-, lateral asymmetric channel (LAC), single event upset (SEU), short channel effects, scaling, SRAM.

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Detailed analysis of FIBL in MOS transistors with high-k gate dielectrics

Abstract: This paper analyzes in detail the Fringing Induced Barrier Lowering (FIBL)

Cited by 13 publications

References 13 publications

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-kgate dielectrics

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-kgate dielectrics

Gate induced drain leakage reduction with analysis of gate fringing field effect on high-κ/metal gate CMOS technology

SEU reliability analysis of advanced deep-submicron transistors

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