The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-kgate dielectrics

Abstract

The fringing-induced barrier lowering (FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator. An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect. The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance. Based on equivalent capacitance theory, the influences of channel length, junction depth, gate/lightly doped drain (LDD) overlap length, spacer material and spacer width on FIBL is thoroughly investigated. A stack gate dielectric is presented to suppress the FIBL effect.

Analysis of Off-State Leakage Current Characteristics and Mechanisms of Nanoscale MOSFETs with a High- k Gate Dielectric

“…These electric lines form an electrical field originating at the drain that penetrates into the channel through the high-𝑘 dielectric and suppresses the barrier height from the source to the channel, thereby causing lower threshold voltage, and increasing off-state current. [14] The change trends of 𝐼 d,leak are consistent with the previous studies. However, when 𝑉 d = 1.0 V, the change of 𝐼 d,leak is different.…”

A threshold voltage model of short-channel fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs with high- k dielectric

“…[16] However, the use of a thicker high-k dielectric material in place of SiO 2 causes considerable fringing-field lines, which in turn modulate the source-channel barrier height, resulting in the change of subthreshold characteristics. [17][18][19][20][21][22][23][24] The effect of fringingfield lines on the subthreshold characteristics of SOI MOS-FET is modeled in terms of a fringing capacitance C bot . [20] The fringing capacitance is attributed to the electric field interaction between the bottom of gate electrode and source/drain region through the side-wall spacer, as shown in Fig.…”