Determination of bulk and interface density of states in polycrystalline silicon thin film transistors

Arpatzanis, N.; Dimitriadis, C. A.; Siskos, S.; Hatzopoulos, A.A.; Kamarinos, G.

doi:10.1016/j.tsf.2006.11.127

Cited by 6 publications

(2 citation statements)

References 11 publications

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“…According to the quantitative values of the de-trapping energy barrier, the MoS 2 TFT exposed to air has a significant number of traps and is more sensitive to charge trapping. We also measured the SCLC in each ambient to determine the contribution of the sub-gap states of the MoS 2 TFT and obtained the interface and bulk trap states using a simple extraction method [39]. Figure 4(a) inset shows the logarithmic I DS -V GS curve measured with a forward gate bias sweep in air at room temperature.…”

Section: Resultsmentioning

confidence: 99%

Quantitative analysis of charge trapping and classification of sub-gap states in MoS₂ TFT by pulse I–V method

2018

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The threshold voltage instabilities and huge hysteresis of MoS thin film transistors (TFTs) have raised concerns about their practical applicability in next-generation switching devices. These behaviors are associated with charge trapping, which stems from tunneling to the adjacent trap site, interfacial redox reaction and interface and/or bulk trap states. In this report, we present quantitative analysis on the electron charge trapping mechanism of MoS TFT by fast pulse I-V method and the space charge limited current (SCLC) measurement. By adopting the fast pulse I-V method, we were able to obtain effective mobility. In addition, the origin of the trap states was identified by disassembling the sub-gap states into interface trap and bulk trap states by simple extraction analysis. These measurement methods and analyses enable not only quantitative extraction of various traps but also an understanding of the charge transport mechanism in MoS TFTs. The fast I-V data and SCLC data obtained under various measurement temperatures and ambient show that electron transport to neighboring trap sites by tunneling is the main charge trapping mechanism in thin-MoS TFTs. This implies that interfacial traps account for most of the total sub-gap states while the bulk trap contribution is negligible, at approximately 0.40% and 0.26% in air and vacuum ambient, respectively. Thus, control of the interface trap states is crucial to further improve the performance of devices with thin channels.

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Section: Resultsmentioning

confidence: 99%

Quantitative analysis of charge trapping and classification of sub-gap states in MoS₂ TFT by pulse I–V method

2018

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“…[1][2][3][4][5][6][7][8] The effective density of traps was extracted from the noise measurements using the McWhorter model. 9 For the SiO 2 gate dielectric, it was within the range from 10 19 to 10 21 ͑cm 3 ev͒ −1 , which is an approximately two orders of magnitude higher than for crystalline Si metaloxide-semiconductor field-effect transistor ͑MOSFETs͒.…”

Section: Introductionmentioning

confidence: 99%

Low frequency noise in amorphous silicon thin film transistors with SiNx gate dielectric

Rumyantsev

Jin

Shur

et al. 2009

Journal of Applied Physics

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The analysis of experimental data following the McWhorter model for the low frequency noise in amorphous Si thin film transistors (TFTs) with SiNx gate dielectric revealed relatively low density of traps Nt≈1019 (cm3 eV)−1. This value is close to the lower limit ever reported for amorphous and polycrystalline Si TFTs. Trap density only slightly increases with the increase of the gate voltage, i.e., approaching the conduction band edge.

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A numerical analysis of the electrical characteristics of small-grains poly-Si TFTs

Touidjen

Mansour

2009

Eur. Phys. J. Appl. Phys.

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Determination of bulk and interface density of states in polycrystalline silicon thin film transistors

Cited by 6 publications

References 11 publications

Quantitative analysis of charge trapping and classification of sub-gap states in MoS₂ TFT by pulse I–V method

Quantitative analysis of charge trapping and classification of sub-gap states in MoS₂ TFT by pulse I–V method

Low frequency noise in amorphous silicon thin film transistors with SiNx gate dielectric

A numerical analysis of the electrical characteristics of small-grains poly-Si TFTs

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Determination of bulk and interface density of states in polycrystalline silicon thin film transistors

Cited by 6 publications

References 11 publications

Quantitative analysis of charge trapping and classification of sub-gap states in MoS2 TFT by pulse I–V method

Quantitative analysis of charge trapping and classification of sub-gap states in MoS2 TFT by pulse I–V method

Low frequency noise in amorphous silicon thin film transistors with SiNx gate dielectric

A numerical analysis of the electrical characteristics of small-grains poly-Si TFTs

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Quantitative analysis of charge trapping and classification of sub-gap states in MoS₂ TFT by pulse I–V method

Quantitative analysis of charge trapping and classification of sub-gap states in MoS₂ TFT by pulse I–V method