Deterministic BIST with multiple scan chains

Kiefer, Gundolf; Wunderlich, Hans-Joachim

doi:10.1109/test.1998.743304

Cited by 48 publications

(25 citation statements)

References 24 publications

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“…The compression ratio for the test data storage requirements is shown. It is computed as : TABLE II COMPARISON OF PROPOSED HYBRID BIST SCHEME WITH BIST FOLLOWED BY TOP-UP TEST PATTERNS FROM TESTER TABLE III COMPARISON OF PROPOSED HYBRID BIST SCHEME WITH DETERMINISTIC BIST SCHEME IN [14] As can be seen, the tester storage requirements are reduced by at least an order of magnitude in all cases with the proposed hybrid BIST approach based on weighted pseudorandom testing. Table III shows a comparison of the area overhead for the proposed hybrid BIST approach compared with the best published results for deterministic BIST in [14] that provides the same fault coverage.…”

Section: Resultsmentioning

confidence: 99%

“…This comparison assumes that a PLA implementation is used. It should be noted that for one or both of the techniques, a multilevel logic implementation may be more efficient than a PLA (this is in fact suggested in [14] for a STUMPS architecture). Also, note that the comparison only considers the area overhead of the PLA.…”

Section: Resultsmentioning

confidence: 99%

“…Also, note that the comparison only considers the area overhead of the PLA. It does not include the area overhead for the STUMPS architecture itself, however, the results in [14] indicate that the PLA area dominates the total area for BIST for these circuits. The compression ratio for the PLA area overhead requirements is shown.…”

Section: Resultsmentioning

confidence: 99%

“…There are two solutions to this problem. One is to modify the circuit to eliminate the random pattern resistance by inserting test points [7], and the other is to modify the test pattern generator by adding additional hardware to generate patterns that detect the hard faults [8], [14], [15], [22]. Both approaches have significant drawbacks.…”

Section: Introductionmentioning

confidence: 99%

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Weighted pseudorandom hybrid BIST

Jas

Krishna

Touba

2004

IEEE Trans. VLSI Syst.

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Abstract-This paper presents a new test data-compression scheme that is a hybrid approach between external testing and built-in self-test (BIST). The proposed approach is based on weighted pseudorandom testing and uses a novel approach for compressing and storing the weight sets. Three levels of compression are used to greatly reduce test costs. Experimental results show that the proposed scheme reduces tester storage requirements and tester bandwidth requirements by orders of magnitude compared to conventional external testing, but requires much less area overhead than a full BIST implementation providing the same fault coverage. No test points or any modifications are made to the function logic. The paper describes the proposed hybrid BIST architecture as well as two different ways of storing the weight sets, which are an integral part of this scheme.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Weighted pseudorandom hybrid BIST

Jas

Krishna

Touba

2004

IEEE Trans. VLSI Syst.

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“…It is a well-known paradigm of the modern circuits design that the testability issues must be reflected already in the design time of a circuit and that the structure of the circuit is modified in order to make the circuit testable. A number of strategies for the "design for testability" have been developed, for instance, BIST, scan techniques, test point insertion and so on [16,7].…”

Section: Fault-tolerant Circuits and Diagnosticsmentioning

confidence: 99%

Easily testable image operators: the class of circuits where evolution beats engineers

Sekanina

Růžička

NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings.

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Using ATPG vectors for BIST test pattern generator

Asakawa

Iwasaki

2001

Systems & Computers in Japan

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SUMMARYAs a solution to improve the characteristics of pseudo-random pattern tests, a BIST-oriented test pattern generator (TPG) designed to achieve complete coverage of stuck-at faults with short test sequences is proposed. In the proposed method, ATPG vector sets are split-shifted to obtain pseudo-random vectors, and such vectors are then used in a mixed test pattern. Since random pattern resistant faults are detected by ATPG vectors, stuck-at faults can be covered completely with a short test sequence. This paper presents the proposed TPG configuration, test pattern generation algorithm, and the selection of the vector set for bit shift. The proposed method is evaluated in terms of test length and hardware overhead by applying it to ISCAS benchmark circuits. © 2001 Scripta Technica, Syst Comp Jpn, 32(11): 18, 2001

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Deterministic BIST with multiple scan chains

Cited by 48 publications

References 24 publications

Weighted pseudorandom hybrid BIST

Weighted pseudorandom hybrid BIST

Easily testable image operators: the class of circuits where evolution beats engineers

Using ATPG vectors for BIST test pattern generator

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