Development of 3-D Stack Package Using Silicon Interposer for High-Power Application

Khan, N.; Yoon, Seung Wook; Viswanath, A.G.K.; Ganesh, V.P.; Nagarajan, Rajamani; Witarsa, D.; Lim, S.; Kripesh, V.

doi:10.1109/tadvp.2008.915854

Cited by 24 publications

(13 citation statements)

References 5 publications

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“…Without compromising processing speed, the integration of multi-chips in one interposer on the package tends to generate higher heat density, which needs to be addressed in the 2.5D or 3D package design. [102][103][104][105][106][107][108][109][110][111][112][113][114][115] A schematic of the cooling concepts is illustrated in Figure 50.…”

Section: Thermal Considerations Of 25d Packagesmentioning

confidence: 99%

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Heterogeneous 2.5D integration on through silicon interposer

Zhang¹,

Lin²,

Wickramanayaka³

et al. 2015

Applied Physics Reviews

129

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Section: Thermal Considerations Of 25d Packagesmentioning

confidence: 99%

“…The cooling of 3D stacked packages with on chips on Si carriers is studied in Ref. 105. It was identified that, due to package limitation, only 1 W could be dissipated from the two chips stacked on their chip carriers through microbump joining.…”

Section: Thermal Considerations Of 25d Packagesmentioning

confidence: 99%

Heterogeneous 2.5D integration on through silicon interposer

Zhang¹,

Lin²,

Wickramanayaka³

et al. 2015

Applied Physics Reviews

129

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“…However, wire bonds have limited ability to dissipate heat and have relatively high parasitic inductance, which often restricts the thermal and electrical performance of the power modules. To overcome this problem, several replacements of wire bonds, such as ribbon bond [1], dimple array [2], embedded chip technology [3]- [5], silicon interposer [6], solder bump [7], metal bump [8]- [12], and press-pack bus-bar-like interconnects [13] have been proposed and investigated over the past years. Of them, metal bump interconnects, also called solid interconnect posts, have been demonstrated not only to obtain dramatic improvement in the thermal and electromagnetic performance, but also allow advanced integration schemes, e.g., stacked devices, for the optimization of basic power switch topologies, e.g., half bridge switch and bidirectional switch [14]- [16].…”

Section: Introductionmentioning

confidence: 99%

Built-in Reliability Design of Highly Integrated Solid-State Power Switches With Metal Bump Interconnects

Castellazzi

Dai

et al. 2015

IEEE Trans. Power Electron.

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A stacked substrate-chip-bump-chip-substrate assembly has been demonstrated in the construction of power switch modules with high power density and good electrical performance. In this paper, special effort has been devoted to material selection and geometric shape of the bumps in the design for improving the thermomechanical reliability of a highly integrated bidirectional switch. Results from 3-D finite-element simulation indicate that for all design cases the maximum von Mises stresses and creep strain accumulations occur in the solder joints used to join bumps on IGBTs during a realistic mission profile, but occur in the solder joints used to join bumps on DBC substrates during accelerated thermal cycling. The results from both the simulation and the accelerated thermal cycling experiments reveal that selection of Cu/Mo/Cu composite brick bumps in the stacked assembly can significantly improve the thermomechanical reliability of both the solder joints and the DBC substrates when compared to Cu cylinder bumps and Cu hollow cylinder bumps reported in previous work. Such results can be attributed to the effective reduction in the extent of mismatch of coefficients of thermal expansion between the different components in the assembly.Index Terms-Cu/Mo/Cu composite, finite-element (FE) method, integration, thermal cycling, wirebond-less packaging.

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“…According to the curvature enhanced accelerator coverage (CEAC) mechanism proposed for copper damascene electroplating process [182,183]…”

Section: Copper Via-filling Processmentioning

confidence: 99%

“…A summary of the wafer back-grinding and polishing parameters is summarized in Table 6.8. The completed silicon carrier wafer is then assembled on board and tested for electrical continuity and via resistance [32,182]. The carriers were tested for thermal cycle reliability condition -40 °C to 125 ºC upto 1000 cycles.…”

Section: (A) (B)mentioning

confidence: 99%

Development and characterization of deep reactive ion etching technology for through silicon interconnection

Nagarajan¹

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Deep reactive ion etching (DRIE) is an enabling technology for three dimensional (3D) integration of planar integrated circuits. This work focuses on various challenges associated with deep reactive ion etching technology for realizing through silicon interconnection for 3D Microsystems application. In the first part of the thesis, stress simulation studies were done on TSV structures of various via geometries and shapes to determine the regions of high stress due to CTE mismatch. It was determined that the top and bottom of the vias and the surrounding materials experience maximum mechanical stress. It was also found that the stress is concentrated in the sharp peaks and valleys of the scallops formed by Bosch etch process. A test vehicle was designed and fabricated by copper damascene process with various geometries and barrier structures to experimentally study the effect of sidewall scallops on electrical leakage between adjacent TSV structures. It was shown that the leakage current can be reduced by about nearly 3 orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall for the initial few microns of the depth of the via by using a non-Bosch etch process. This study has shown that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, for vertical TSV etch application by tailoring a short first etch step with smooth sidewall. In the second part of the research, tapered TSV etching technology was developed and characterized for TSV with diameters of 20-100 µm and depth of 100-300 µm for advanced 3D-Packaging application. In this study, the evolution of tapered via etch topography was modeled for various via diameters and experimentally validated within 5-ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library Development and characterization of deep reactive ion etching technology for through silicon interconnection v 10% deviation. It was also experimentally shown that by combining Bosch, RIE and Isotropic etch processes into a multi-step etch process it is possible to achieve acceptable tapered profile of 83-87º and depth from 200-300µm. It was finally demonstrated that a void-free TSV can be formed with good electrical isolation and electrical continuity. In the third part of the work the influence of deep silicon via profile and sidewall roughness on the electrical conduction through the TSV dielectric was studied. Based on extensive experimental characterization it was shown that the sidewall scallops due to Bosch process and curvature defects due to RIE process strongly influences the dielectric conduction in TSV. It was also shown that the scallops and curvature defects causes defectinduced PF type of leakage mechanism between TSVs. It was further shown that smoothening the sidewall defects at top results in significant reduction in leakage current by 3-5 order of magnitude. In conclusion, this research work addressed the critical TSV etch challenges and ...

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Development of 3-D Stack Package Using Silicon Interposer for High-Power Application

Cited by 24 publications

References 5 publications

Heterogeneous 2.5D integration on through silicon interposer

Heterogeneous 2.5D integration on through silicon interposer

Built-in Reliability Design of Highly Integrated Solid-State Power Switches With Metal Bump Interconnects

Development and characterization of deep reactive ion etching technology for through silicon interconnection

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