Development of a Layout-Level Hardware Obfuscation Tool

Malik, Shweta; Becker, Georg T.; Paar, Christof; Burleson, Wayne

doi:10.1109/isvlsi.2015.118

Cited by 29 publications

(18 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For a more meaningful comparison, we also consider relatively small scales for LC (10% up to 30%). Here, the primitive advocated by Zhang [11] appears as the weakest, and the one proposed by Malik et al [41] seems the most resilient. Our primitive is next only to that of Wang et al [10] and that of Malik et al [41].…”

Section: B Security Evaluationmentioning

confidence: 90%

“…Here, the primitive advocated by Zhang [11] appears as the weakest, and the one proposed by Malik et al [41] seems the most resilient. Our primitive is next only to that of Wang et al [10] and that of Malik et al [41]. Now, it is also important to recall that our proposed technique incurs significantly smaller PPA cost than these schemes [10], [41].…”

Section: B Security Evaluationmentioning

confidence: 90%

See 1 more Smart Citation

Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging

Patnaik¹,

Ashraf²,

Knechtel³

et al. 2017

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

View full text Add to dashboard Cite

Abstract-Layout camouflaging (LC) is a promising technique to protect chip design intellectual property (IP) from reverse engineers. Most prior art, however, cannot leverage the full potential of LC due to excessive overheads and/or their limited scope on an FEOL-centric and accordingly customized manufacturing process. If at all, most existing techniques can be reasonably applied only to selected parts of a chipwe argue that such "small-scale or custom camouflaging" will eventually be circumvented, irrespective of the underlying technique.In this work, we propose a novel LC scheme which is low-cost and generic-full-chip LC can finally be realized without any reservation. Our scheme is based on obfuscating the interconnects (BEOL); it can be readily applied to any design without modifications in the device layer (FEOL). Applied with split manufacturing in conjunction, our approach is the first in the literature to cope with both the FEOL fab and the enduser being untrustworthy. We implement and evaluate our primitives at the (DRC-clean) layout level; our scheme incurs significantly lower cost than most of the previous works. When comparing fully camouflaged to original layouts (i.e., for 100% LC), we observe on average power, performance, and area overheads of 12%, 30%, and 48%, respectively.Here we also show empirically that most existing LC techniques (as well as ours) can only provide proper resilience against powerful SAT attacks once at least 50% of the layout is camouflaged-only large-scale LC is practically secure. As indicated, our approach can deliver even 100% LC at acceptable cost. Finally, we also make our flow publicly available, enabling the community to protect their sensitive designs.

show abstract

Section: B Security Evaluationmentioning

confidence: 90%

Section: B Security Evaluationmentioning

confidence: 90%

Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging

Patnaik¹,

Ashraf²,

Knechtel³

et al. 2017

2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

View full text Add to dashboard Cite

show abstract

“…Another method to conceal connections is through adding connections through diffusion [10]. By doing so, one can create inverters that are stuck at a logic one, or a logic zero.…”

Section: Obfuscated Defensesmentioning

confidence: 99%

“…The disadvantage of this approach is a large increase in area and delay. One paper reported that this approach increased the area by 587% and the delay by 250% [10].…”

Section: Obfuscated Defensesmentioning

confidence: 99%

Digital IP protection using threshold voltage control

Davis

Kulkarni

Yang

et al. 2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

View full text Add to dashboard Cite

Abstract-This paper proposes a method to completely hide the functionality of a digital standard cell. This is accomplished by a differential threshold logic gate (TLG). A TLG with n inputs implements a subset of Boolean functions of n variables that are linear threshold functions. The output of such a gate is one if and only if an integer weighted linear arithmetic sum of the inputs equals or exceeds a given integer threshold. We present a novel architecture of a TLG that not only allows a single TLG to implement a large number of complex logic functions, which would require multiple levels of logic when implemented using conventional logic primitives, but also allows the selection of that subset of functions by assignment of the transistor threshold voltages to the input transistors. To obfuscate the functionality of the TLG, weights of some inputs are set to zero by setting their device threshold to be a high Vt. The threshold voltage of the remaining transistors is set to low Vt to increase their transconductance. The number of low Vt transistors whose gates are driven by a given input xi determines the weight of that input. The function of a TLG is not determined by the cell itself but rather the signals that are connected to its inputs. This makes it possible to hide the support set of the function by essentially removing some variable from the support set of the function. This is done by selective assignment of high and low Vt to the input transistors. We describe how a standard cell library of TLGs can be mixed with conventional standard cells to realize complex logic circuits, whose function can never be discovered by reverse engineering. A 32-bit Wallace tree multiplier and a 28-bit 4-tap filter were synthesized on an ST 65nm process, placed and routed, then simulated including extracted parastics with and without obfuscation. By obfuscating the cells the delay was shown to increase by approximately 5% at the cell level. Both obfuscated designs had much lower area (25%) lower area and much lower dynamic power (30%) than their nonobfuscated CMOS counterparts, operating at the same frequency.

show abstract

“…The main defence strategy of the designer is hardware obfuscation to prevent such invasive attacks [5]. Over the last few years, several device, circuit, and system level obfuscation methods have been proposed [6][7][8]. Physical design obfuscation is one that creates stealthy manipulations by changing doping concentration and dielectric material which grabbed recent attention, as it is hard to apply RE [9,10].…”

Section: Introductionmentioning

confidence: 99%

Tunnel FET ambipolarity‐based energy efficient and robust true random number generator against reverse engineering attacks

Japa

Majumder

Sahoo

et al. 2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

This study presents a true random number generator (TRNG) harvesting random bits from delay variations of ambipolarity-based ring oscillator, designed using 20 nm InAs Tunnel FET (TFET). Exploiting the TFET transmission gate (TG) functional failure, TFET ambipolarity-based ring oscillator design has been proposed. Random variations are observed in the oscillating frequency of proposed ring oscillator by changing the TFET device ambipolarity. Exploring the same, a TFET ambipolarity-based TRNG circuit has been demonstrated. XOR gate-based post-processing unit is designed to further enhance the unpredictability and randomness of the output bits. The proposed TRNG has passed various NIST tests performed at a supply voltage of 0.5 V. In 20 nm, the proposed TFET TRNG has an area as low as 90 pm 2 and consumes 5.4 pJ/bit at 0.5 V supply voltage. Ambipolarity-based circuit design makes the proposed TRNG robust against reverse engineering attacks.

show abstract

Development of a Layout-Level Hardware Obfuscation Tool

Cited by 29 publications

References 4 publications

Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging

Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging

Digital IP protection using threshold voltage control

Tunnel FET ambipolarity‐based energy efficient and robust true random number generator against reverse engineering attacks

Contact Info

Product

Resources

About