Development of air-gap etching process by a mask approach for characterization of intralayer and interlayer capacitances

Abstract

An air-gap structure was implemented in the metal 2 (M2) layer of a copper interconnect by a mask approach. The fabrication of the air-gap was achieved by tuning etching process parameters such as temperature and etchant chemistry. A residue-free copper surface was realized by optimizing the different steps in the air-gap etching process. The M2 intralayer and interlayer capacitances were measured by using the charge-based capacitance measurement (CBCM) technique and compared with the simulation. Results show that, after the air-gap etching process, with the deposition of 150 Å SiCN on the M2 line with a width of 90 nm, a 22% intralayer capacitance drop was found in the M2 and the 16% ring oscillator frequency was improved. An increase in interlayer capacitance was observed, which resulted from the SiCN thickness decrease on the M2 layer and without the use of dielectric planarization after air-gap formation.