Development of compact thermal models for advanced electronic packaging: methodology and experimental validation for a single-chip CPGA package

Aranyosi, A.; Ortega, Alfonso; Evans, John L.; Tarter, T.; Pursel, J.; Radhakrishnan, Jagadeesh

doi:10.1109/itherm.2000.866829

Cited by 13 publications

(5 citation statements)

References 8 publications

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“…A remarkable and unexpected result: at least for this TQFP, the "99" set can be reduced to a "9" set without a significant loss in accuracy. Aranyosi et al 6 jumped to the same conclusion. Table 4.18 shows the errors for various subsets, defined as sets describing a certain application field, such as free convection only.…”

Section: "38" and "99" Sets Reduced Sets And Subsets Dotcomp Tqfpmentioning

confidence: 82%

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Boundary-Condition-Independent Compact Models

Lasance

Sabry

Bar‐Cohen

2014

Encyclopedia of Thermal Packaging

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This chapter gives a complete survey of resistive network type BCI compact thermal models. Several benchmarks representing different package families are discussed, how exactly BCI models are generated via optimization starting from detailed models, including how the topology is selected, how the cost function is defined, what the level of accuracy is, what the differences are between various optimization techniques, and especially to which accuracy the compact models should be compared. The Chapter is closed with a discussion of papers from other than DELPHI sources.

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Section: "38" and "99" Sets Reduced Sets And Subsets Dotcomp Tqfpmentioning

confidence: 82%

“…Unfortunately, there seems no way to judge a priori which boundary conditions to choose, except for the fact that some extremes should be included. It was also demonstrated by Aranyosi et al 6 that a much smaller set is sufficient to generate BCI models.…”

Section: The "99" Boundary Condition Setmentioning

confidence: 96%

Boundary-Condition-Independent Compact Models

Lasance

Sabry

Bar‐Cohen

2014

Encyclopedia of Thermal Packaging

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“…Lasance (1997) has provided reviews of the development of the compact thermal modeling methodology. Other studies (Aranyosi et al 2000) have examined how design of experiments can be used in order to select an appropriate set of boundary conditions under which the initial thermal response tests should be conducted.…”

Section: R Ijmentioning

confidence: 99%

A parameter optimization heuristic for a temperature estimation model

et al. 2008

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We present a heuristic technique for solving a parameter estimation problem that arises in modeling the thermal behavior of electronic chip packages. Compact Thermal Models (CTMs) are network models of steady state thermal behavior, which show promise in augmenting the use of more detailed and computationally expensive models. The CTM parameter optimization problem that we examine is a nonconvex optimization problem in which we seek a set of CTM parameters that best predicts, under general conditions, the thermal response of a particular chip package geometry that has been tested under a small number of conditions. We begin by developing a nonlinear programming formulation for this parameter optimization problem, and then develop an algorithm that uses special characteristics of the optimization problem to quickly generate heuristic solutions. Our algorithm descends along a series of solutions to one-dimensional nonconvex optimization problems, obtaining a locally optimal set of model parameters at modest computational cost. Finally, we provide some experimental results and recommendations for extending this research.

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“…The detailed BGA model faithfully reproduced the ,geometry that was experimentally validated in [9]. This provided an experimentally validated test package and board and a detailed report of all thermophysical properties and assumptions.…”

Section: Package Compact Model Generationmentioning

confidence: 72%

“…The ball grid array package specifications adopted duplicated the package model utilized in a recent JEDEC standardization exercise [8,9]. The detailed BGA model faithfully reproduced the ,geometry that was experimentally validated in [9].…”

Section: Package Compact Model Generationmentioning

confidence: 99%

An investigation of board level effects on compact thermal models of electronic chip packages

DeVoe

Ortega²

Eighteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium. Proceedings 2002 (Cat.No.02CH37311)

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The application and use of Compact Thermal Models of single chip electronic packages in a board level environment has seen limited study. In particular the influence of board thermal characteristics on the predictive accuracy of CTMs generated independently of the board is not well understood. A systematic study of the influence of board conduction on the predictive accuracy of Compact Thermal Models of BGA and CPGA package styles was performed. For the CPGA special attention was given to the socket model. The compact model parameters were extracted using a standard optimization procedure to best reproduce the junction temperature and heat flows computed for the detailed models exposed to a reduced set of heat transfer coefficients on the prime lumped areas. Various resistance network topologies were assessed for each package style. Detailed (FE) isotropic board models with conductivities spanning three orders of magnitude were created to test the influence of board conductivity on CTM accuracy. The board models included fully detailed isotropic models of the lSOP and 1S2P JEDEC standard thermal test boards. Compact models were deployed on these detailed board models with the board surfaces exposed to a wide variety of convective cooling conditions to test the limits of the package models. Results were compared to equivalent fully-detailed (FE) package models on detailed board models. The predictive capability of the optimized topologies was strongly correlated to the existence of strong local temperature gradients in the board, whenever the sensitivity to board heat conduction was high. When the board is poorly conducting (k=l W/m-K), board heat conduction is too low to matter. When the board is highly conducting (k=lOO W/m-K), the high conductivity smooths out local board temperature gradients, and the CTMs are accurate even though the board heat flow path is dominant.For intermediate board thermal conductivities of order 10 W/m-K, the heat conduction into the board is significant enough to cause sensitivity, and the conductivity is low enough to allow significant board temperature gradients. These conditions significantly degrade the predictive accuracy of CTMs.In general, optimized network topologies that included shunt resistances were found to predict the junction temperature to within 5% to 8% over a wide range of board conductivities, while star-shaped networks were generally only accurate to 10-15%. detailed model, printed circuit board, network topology

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Development of compact thermal models for advanced electronic packaging: methodology and experimental validation for a single-chip CPGA package

Cited by 13 publications

References 8 publications

Boundary-Condition-Independent Compact Models

Boundary-Condition-Independent Compact Models

A parameter optimization heuristic for a temperature estimation model

An investigation of board level effects on compact thermal models of electronic chip packages

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