IEEE International Electron Devices Meeting 2003
DOI: 10.1109/iedm.2003.1269360
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Device design considerations for ultra-thin SOI MOSFETs

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Cited by 47 publications
(33 citation statements)
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“…According to the International Technology Roadmap for Semiconductors (ITRS), production-stage MOSFETs with gate lengths around 20 nm and below 10 nm will be needed in the years 2009 and 2016, respectively [1]. Recently, MOSFETs with sub-10 nm gates showing regular transistor operation have been successfully fabricated in different laboratories see, e.g., [2][3][4]. These devices, however, by far do not meet the ITRS performance targets, such as the onand off-currents I on and I off .…”
Section: Introductionmentioning
confidence: 99%
“…According to the International Technology Roadmap for Semiconductors (ITRS), production-stage MOSFETs with gate lengths around 20 nm and below 10 nm will be needed in the years 2009 and 2016, respectively [1]. Recently, MOSFETs with sub-10 nm gates showing regular transistor operation have been successfully fabricated in different laboratories see, e.g., [2][3][4]. These devices, however, by far do not meet the ITRS performance targets, such as the onand off-currents I on and I off .…”
Section: Introductionmentioning
confidence: 99%
“…The introduction of high-mobility III-V materials in MOSFETs requires new device concepts which can benefit from the high channel mobility with scaling. These new device concepts have to be based on a thin body architecture due to its superior electrostatic integrity and higher channel mobility resulting from low-dimensional transport [12], [13]. The design and particularly the vertical device architecture have to be optimized with respect to the channel material and its orientation bearing in mind that at small channel thicknesses the mobility is degraded due to enhanced scattering of carriers with confined phonons [14].…”
Section: Introductionmentioning
confidence: 99%
“…A number of different designs are under consideration for sub 10 nm gate length transistors. The use of very thin silicon on insulator substrates has already lead to working transistors with 6 nm gate lengths [20,21]. Another means of increasing drive current is to increase the area of the gate electrode through either multiple gates or wrap-around gates.…”
Section: Trend: Modeling Will Be An Increasingly Important Means Of Cmentioning
confidence: 99%
“…Recently, Price, et al, developed the application of the Cody Lorentz model for high-k materials [21]. The improved VUV response of this model allows the interface and high-k layers to be measured separately using spectroscopic ellipsometry.…”
Section: Trend: Interfacial Measurement and Control Is Increasing In mentioning
confidence: 99%