Device reliability under electrical stress and photo response of oxide TFTs

Abstract

Abstract— The stability of oxide TFTs has been the main focus of this research and is probably the most crucial requirement for the successful application to flat‐panel displays. Although the high Fermi level of oxide semiconductors makes TFTs basically stable under electrical stress, the device reliability under diverse variations of electrical stress is affected by materials such as active semiconductors and gate insulators, processes for the formation of back/front channels and passivation layers, and device configurations among other things. How these factors affect the device reliability have been investigated and a review of the stability is presented. In addition, several categories of the light instability of oxide TFTs is presented and the origin is discussed.

Multifunctionality of Giant and Long-Lasting Persistent Photoconductivity: Semiconductor–Conductor Transition in Graphene Nanosheets and Amorphous InGaZnO Hybrids

“…41 44 Here, we investigate the TFT stability dependence on lightinduced effects. Comparing Figure 2a and b, with focus on 350 nm UV light, the GNSs/a-IGZO TFTs exhibit a remarkable shift in V th , with a negative ΔV th of 7.22 V for GNSs/a-IGZO TFTs, which is much larger than that of 4.01 V for a-IGZO TFTs.…”

“…These highly localized holes cannot easily escape from the trapping centers and recombine with free electrons. 41 As a consequence, this leads to the very long recovery time of the photocurrent, the large ΔV th , and the much more pronounced photoconductivity after turning off the light illumination. Conversely, the PPC can be eliminated by releasing the trapped carriers through recombination with carriers of the opposite sign.…”

Performance and Stability Enhancement of In–Sn–Zn–O TFTs Using SiO2 Gate Dielectrics Grown by Low Temperature Atomic Layer Deposition

“…Under PBS, the threshold voltage shift (Δ V th ) of the PEALD SiO 2 TFT is 1.1 V, while the thermal SiO 2 and PECVD SiO 2 devices undergo net Δ V th values of 2.0 and 1.8 V, respectively (Figure c). Positive shifts of the threshold voltage are generally attributed to the trapping of electrons near the gate insulator/semiconductor interface, and here the major trap sites may be associated either with oxygen deficiency-related sites or interstitial oxygen in the ITZO active layer. − In addition, a drop in field effect mobility by approximately 20% is observed after PBS in the PECVD SiO 2 device, while only minor decreases by 6 and 3% only are observed in the thermal and PEALD SiO 2 TFTs. This phenomenon suggests that the creation of defects may be an important mechanism that determines the degradation of the PECVD SiO 2 TFTs, while charge trapping appears to be dominant in the thermal and PEALD SiO 2 devices .…”

“…Previous studies indicate that hydrogen emanating from the gate insulator may first passivate the defects associated with interstitial oxygen sites, followed by the excess hydrogen contributing additional free electrons after post annealing . Further theoretical investigations indicate that hydrogen may passivate electron traps that are associated with interstitial oxygen in oxide semiconductors. ,, As far as hydrogen is concerned, Hosono’s group has reported some papers stating that hydrogen may passivate electron traps. The incorporation of hydrogen by wet oxygen annealing enhanced the recovery of deteriorated TFTs.…”

P.18: Effects of Interface and Bulk States on the Stability of Amorphous InGaZnO Thin Film Transistors under Gate Bias and Temperature Stress

“…The maximum D it value for sample B was much higher than those of samples A and C, which was consistent with the above results. Compared with the fabrication processes for three devices, for sample B，the introduction of oxygen flow to produce oxygenrich a-IGZO film could induce more traps at the channel layergate insulator interface due to the ion bombardment of oxygen plasma [14]. Thus, a lower interface trap density could be obtained by using oxygen-poor a-IGZO film as the front-channel layer, which appeared to be as a buffer layer for sample C.…”