Diagnosis and Layout Aware (DLA) Scan Chain Stitching

Ye, Jing; Huang, Yu; Hu, Yu; Cheng, Wu-Tung; Guo, Ruifeng; Lai, Liyang; Tai, Ting-Pu; Li, Xiaowei; Changchien, Weipin; Lee, Daw-Ming; Chen, Ji-Jan; Eruvathi, Sandeep C.; Kumara, Kartik K.; Liu, Charles; Pan, S.C.

doi:10.1109/tvlsi.2014.2313563

Cited by 15 publications

(2 citation statements)

References 20 publications

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“…The concept of a sensitive cell has been studied previously. Scan-chain reordering [ 36 , 37 ] and stitching [ 38 ] have been proposed to consider logic dependency and controllability between scan cells, where scan-chain diagnosis was improved using a circuit structure. In particular, using the fan-in and fan-out dependencies between scan cells, these methods distributed sensitive cells to other chains, thereby obtaining more clues from failure logs.…”

Section: Motivationsmentioning

confidence: 99%

Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks

Lim

Cheong

Kang

2020

Sensors

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Scan structures, which are widely used in cryptographic circuits for wireless sensor networks applications, are essential for testing very-large-scale integration (VLSI) circuits. Faults in cryptographic circuits can be effectively screened out by improving testability and test coverage using a scan structure. Additionally, scan testing contributes to yield improvement by identifying fault locations. However, faults in circuits cannot be tested when a fault occurs in the scan structure. Moreover, various defects occurring early in the manufacturing process are expressed as faults of scan chains. Therefore, scan-chain diagnosis is crucial. However, it is difficult to obtain a sufficiently high diagnosis resolution and accuracy through the conventional scan-chain diagnosis. Therefore, this article proposes a novel scan-chain diagnosis method using regression and fan-in and fan-out filters that require shorter training and diagnosis times than existing scan-chain diagnoses do. The fan-in and fan-out filters, generated using a circuit logic structure, can highlight important features and remove unnecessary features from raw failure vectors, thereby converting the raw failure vectors to fan-in and fan-out vectors without compromising the diagnosis accuracy. Experimental results confirm that the proposed scan-chain-diagnosis method can efficiently provide higher resolutions and accuracies with shorter training and diagnosis times.

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Section: Motivationsmentioning

confidence: 99%

Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks

Lim

Cheong

Kang

2020

Sensors

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“…Attack Infrastructure: Like other attacks on logic encryption, our proposed attack also requires an encrypted netlist and an activated IC. The attack assumes that the design contains flip-flops and the activated IC has DfT infrastructure [32], [33] (i.e. in full scan environment, all flip-flops get replaced by scan flip-flops, and are connected in a chain) for the purpose of infield testing and debugging.…”

Section: Proposed Scan Based Attack On Logic Encryptionmentioning

confidence: 99%

Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits

Karmakar,

Chatopadhyay,

Kapur

2018

Preprint

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Logic Encryption is one of the most popular hardware security techniques which can prevent IP piracy and illegal IC overproduction. It introduces obfuscation by inserting some extra hardware into a design to hide its functionality from unauthorized users. Correct functionality of an encrypted design depends upon the application of correct keys, shared only with the authorized users. In the recent past, extensive efforts have been devoted in extracting the secret key of an encrypted design. At the same time, several countermeasures have also been proposed by the research community to thwart different state-of-the-art attacks on logic encryption. However, most of the proposed countermeasures fail to prevent the powerful SAT attack. Although a few researchers have proposed different solutions to withstand SAT attack, those solutions suffer from several drawbacks such as high design overheads, low output corruptibility, and vulnerability against removal attack. Almost all the known logic encryption strategies are vulnerable to scan based attack. In this paper, we propose a novel encryption technique called Encrypt Flip-Flop, which encrypts the outputs of selected flip-flops by inserting multiplexers (MUX). The proposed strategy can thwart all the known attacks including SAT and scan based attacks. The scheme has low design overhead and implementation complexity. Experimental results on several ISCAS'89 and ITC'99 benchmarks show that our proposed method can produce reasonable output corruption for wrong keys.

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Introduction

Yan

Liu

2023

Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design

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Diagnosis and Layout Aware (DLA) Scan Chain Stitching

Cited by 15 publications

References 20 publications

Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks

Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks

Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits

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