Dielectric Materials for Advanced VLSI and ULSI Technologies

Abstract

Advancements in very‐large‐scale integration (VLSI) and ultra‐large‐scale integration (ULSI) of semiconductor devices result in complex, multilevel interconnect schemes and increased dependence on dielectric materials. These material systems (how the various materials in an integrated circuit [IC] are united together) are used in a variety of thin‐film applications, such as insulators, ion implanting, and pattern‐etch masking, as well as in final device passivation. For such applications, thin films must exhibit good mechanical, chemical, and electrical properties that are compatible with IC processing schemes. Thin films must also meet ease‐of‐manufacturing requirements. These stringent demands require a clear understanding of the material systems used in advanced technologies. Therefore, dielectric materials are selected according to applications, deposition process and hardware, film properties, and device integration. Thin‐film deposition techniques, including plasma‐enhanced, low‐pressure thermal, electron‐cyclotron‐resonance chemical vapor, and spin‐on are presented. Emerging deposition processes and new dielectrics are also discussed.

Influence of underlying interlevel dielectric films on extrusion formation in aluminum interconnects

“…[1][2][3] These films are usually deposited at high temperatures so that mechanical stress is generated in both the ILD and metal layers due to the difference of thermal expansion coefficients and macroscopic Young's modulus between different layers and the Si substrate. When it arises in ULSI metallization and passivation systems, this stress can lead to metal line voiding, hillocks, extrusions, cracking, poor adhesion, delamination, and eventually complete mechanical failure of the circuit.…”

Combined Surface-Activated Bonding Technique for Low-Temperature Cu/SiO2 Hybrid Bonding

“…For a variety of manufacturability issues, sub-atmospheric chemical vapor deposited ozone-tetraethyl orthosilicate (SACVD O 3 -TEOS) films are frequently used as the isolation liner dielectric in the high aspect ratio vias of Cu-TSV’s. [17] However, O 3 -TEOS films are notoriously hygroscopic,[18] and known to contain significant concentrations of electrically active defects. [19] There are numerous reliability challenges in using O 3 -TEOS; for example, the time dependent dielectric breakdown (TDDB) lifetime of such O 3 -TEOS liner is far below ten years due to the degradation of the liner, accompanied by the release of byproducts such as water and hydrogen.…”

Study of the properties of thin films of silicon nitride and silicon oxide using effective medium theories

“…3 Silicon nitride is widely used for the passivation of silicon-based devices, as a gate dielectric in metal-nitride-silicon structures, as an oxidation mask in planar structures, and in the fabrication of microsensors. Silicon oxide films are generally used as passivation layers for power bipolar transistors.…”