Advancements in very‐large‐scale integration (VLSI) and ultra‐large‐scale integration (ULSI) of semiconductor devices result in complex, multilevel interconnect schemes and increased dependence on dielectric materials. These material systems (how the various materials in an integrated circuit [IC] are united together) are used in a variety of thin‐film applications, such as insulators, ion implanting, and pattern‐etch masking, as well as in final device passivation. For such applications, thin films must exhibit good mechanical, chemical, and electrical properties that are compatible with IC processing schemes. Thin films must also meet ease‐of‐manufacturing requirements. These stringent demands require a clear understanding of the material systems used in advanced technologies. Therefore, dielectric materials are selected according to applications, deposition process and hardware, film properties, and device integration. Thin‐film deposition techniques, including plasma‐enhanced, low‐pressure thermal, electron‐cyclotron‐resonance chemical vapor, and spin‐on are presented. Emerging deposition processes and new dielectrics are also discussed.

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The dielectric quality (defect density, Do and breakdown strength, Fbd) of 150Å SiO2 gate oxide (GOX) films grown by conventional or stacked oxidation scheme are discussed from the leakage measurements of polysilicon capacitors on test structure simulating our submicron CMOS process. Various polysilicon (poly) deposition processes from silane pyrolysis (570°C -620°C) were used by the low pressure chemical vapor deposition (LPCVD) technique. Both in situ and ex situ poly doping by phosphorus (P) were used to ascertain their impact on the GOX properties. The substructural characteristics of the poly/SiO2 and SiO2/Si interfaces generated by various combinations of GOX and poly deposition processes were done by the high resolution TEM lattice fringe technique under phase contrast mode.

New materials are opening the way for advanced VLSI and ULSI technologies.

Rapid Thermal Processors (RTP) have been used in the semiconductor industry mainly for silicidation and implant anneal with limited success. RTP has been projected as a potential tool for years to be used for high temperature processes such as oxidation, junction annealing especially with low thermal budgets. The main handicap of these systems is the difficulty in measuring and controlling the temperature to the required specification. SEMATECH is in the process of establishing a joint development project (JDP) with supplier community to improve the situation. To understand the capability of the tools, a benchmark experiment was conducted using oxidation at 1 100°C (target 90 A), and Boron implant (5E 15 @ 20 KeV) anneal at 900°C for 20 sec. Oxide thickness and sheet resistance were measured as an indirect capability of temperature measurement and control of the tools. The experiments in RTP were performed with 'pyrometer closed-loop control' and 'open-loop power control' where applicable. Both process data and temperature measurement data are analyzed and presented. The wafers used for this experiment were 200 mm size, with varied backside films. The analysis of oxide thickness and sheet resistance (implant anneal) data shows that the closed-loop pyrometer control of temperature is not a viable technique to use in the manufacturing. The power control technique with the pyrometer in the open-loop (read only) demonstrates better process control and can be used until more viable technique is found. The reproducibility of open-loop power control technique for longer periods needs to be evaluated. This study demonstrates the urgent need to develop a real time temperature measurement and control technique for the RTP tools to be accepted in the manufacturing world.