Digital-domain chopping technique for high-resolution PLL-based sensor interfaces

Abstract

Due to their high compatibility with scaled CMOS and emerging technologies, highly-digital time-based architectures, such as PLL-based architectures, have become an attractive alternative to amplitude-based circuits for sensor interfaces, in terms of high time resolution and the potential for low power and area scalability. Although quantization and thermal noise in PLL-based architectures can be addressed by applying noise shaping and oversampling, offset and 1/f noise limit the resolution at high oversampling ratios. Therefore, dynamic offset cancellation techniques such as chopping and autozeroing, as used in traditional amplitude-based circuits, must be adapted to such time-based implementations as well. This paper presents a digital-domain chopping technique suited for offset and 1/f-noise cancellation in applications where medium-tohigh-resolution sensor interfaces are needed. System-level simulations demonstrate the benefits of this technique at high oversampling ratios. The resolution improvement is confirmed by measurements, showing the rate of 10dB of SNR gain per decade of oversampling as expected from theory.

Performance Limitation Analysis of Highly-Digital Time-Based Closed-Loop Sensor-to-Digital Converter Architectures

“…The architecture consists of two matched VCOs and a multi-bit phase detector (PD). A time-domain chopping technique introduced in [13] is employed to cancel both the DC offset from the VCOs' mismatch and the VCOs' 1/f noise. Note that the multi-bit PD can be substituted by a single-bit PD and a digital PI filter to create an N -bit output, resulting in an almost equivalent system [14], avoiding the multi-bit PD nonlinearity.…”

“…The two time-based closed-loop architectures studied here theoretically have similar performance. However, the PLL-based system requires matched VCOs [14]; time-domain chopping relaxes this requirement [13]. The count-based topology intrinsically avoids this demand by employing only one VCO, which also leads to a lower power consumption.…”

“…Here, multiphase VCO outputs or VCOs in combination with counters are used as quantizers following power-hungry loop filters. PLL-based sensor-to-digital interface architectures have been described in [11]- [13]. In [14], a theoretical study shows Manuscript received X XX, XXXX; revised X XX, XXX.…”

“…In this brief only the 1/f 2 oscillator noise is considered. The 1/f noise can be canceled by means of chopping[13] in a PLL-based architecture. In a count-based architecture, the VCO flicker noise can be tackled by means of negative feedback[17].…”

Frequency-Based Sensor Interface with Dynamic Offset Compensation

“…Time domain chopping techniques combined with VCO tuning were applied to PLLbased sensor to digital converters to address the effect of dynamic offsets in [12][13][14]. The VCO tuning technique is aimed at reducing the residual offset after the chopping process.…”