2011
DOI: 10.1109/led.2011.2159475
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Drain-Induced Barrier Lowering in Short-Channel Poly-Si TFT After Off-Bias Stress Using Metal-Induced Crystallization of Amorphous Silicon

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Cited by 11 publications
(10 citation statements)
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“…Additionally, the LS coverage of th2 S/D region has obvious impact on the drain current, since number 1 device shows much lower current than number 3 device, while number 2 and 3 device show similar drain current. It may be explained by the vertical electrical field between S/D region and the LS layer changes the electrical field distribution in the channel [7] [8]. The result shown in Table.1 and Figure.5 proves that number 2 device has more stable behavior in terms of threshold voltage and output performance.…”
Section: Theorymentioning
confidence: 85%
“…Additionally, the LS coverage of th2 S/D region has obvious impact on the drain current, since number 1 device shows much lower current than number 3 device, while number 2 and 3 device show similar drain current. It may be explained by the vertical electrical field between S/D region and the LS layer changes the electrical field distribution in the channel [7] [8]. The result shown in Table.1 and Figure.5 proves that number 2 device has more stable behavior in terms of threshold voltage and output performance.…”
Section: Theorymentioning
confidence: 85%
“…5, the energy barrier in the back of the channel becomes increasingly low as the drain-source voltage increases, owing to the electric field induced by the drain-source voltage, commonly called the DIBL effect, which commonly appears in a short channel device, and it occurs after the application of off-state stress. [18,19] For a device with a shorter channel 027101-3 length, the voltage across the drain and source (V DS ) is increased, more field lines penetrate into the inside of the channel from the drain end. [18] Due to the electric field penetration, the barrier height around the channel is lowered, [18,19] finally allowing electrons from the source region to punch through the buffer layer over the reduced barrier, resulting in buffer leakage currents in both devices.…”
Section: Discussionmentioning
confidence: 99%
“…[18,19] For a device with a shorter channel 027101-3 length, the voltage across the drain and source (V DS ) is increased, more field lines penetrate into the inside of the channel from the drain end. [18] Due to the electric field penetration, the barrier height around the channel is lowered, [18,19] finally allowing electrons from the source region to punch through the buffer layer over the reduced barrier, resulting in buffer leakage currents in both devices. By comparing Fig.…”
Section: Discussionmentioning
confidence: 99%
“…All the a-IGZO TFTs exhibit typical transistor behavior with no drain-induced barrier lowering effect. [50,51] The field-effect mobility (µ FE ) curves are also shown in Figure 2a-e for the respective devices. The a-IGZO TFT with no passivation exhibits the µ FE of 17.13 cm 2 V −1 s −1 , V TH of 1.11 V, and subthreshold swing (SS) of 115 mV dec −1 , as shown in Figure 2a.…”
Section: Sputtered A-igzo Tfts With Single and Stack Passivation Layersmentioning
confidence: 99%