Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage

Natsui, Masanori; Tamakoshi, Akira; Honjo, Haruo; Watanabe, Takahiro; Nasuno, T.; Zhang, C.; Tanigawa, T.; Inoue, Hirofumi; Niwa, Miki; Yoshiduka, T.; Noguchi, Y.; Yasuhira, M.; Ma, Yi; Shen, Hung Tao; Fukami, Shunsuke; Sato, Hideo; Ikeda, Shoji; Ohno, Hideo; Endoh, Tetsuo; Hanyu, Takahiro

doi:10.1109/vlsicircuits18222.2020.9162774

Cited by 18 publications

(6 citation statements)

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“…After the discovery of STT, the STT-driven MRAM significantly reduces the energy of MRAM devices, and the transition of MTJs from in-plane to perpendicular anisotropy improves the thermal stability and device density. After 2020, new technology of SOT-MRAM integrated with CMOS circuits has been demonstrated, [44,45] with much higher endurance and much faster writing speed.…”

Section: Main Progressmentioning

confidence: 99%

From microelectronics to spintronics and magnonics

Han¹,

Wan²,

Wu³

et al. 2022

Chinese Phys. B

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In this review, the recent progresses in microelectronics, spintronics and magnonics have been summarized and compared. Firstly, the history of the spintronics has been briefly reviewed. Moreover, the recent development of magnonics such as magnon-mediated current drag effect (MCDE), magnon valve effect (MVE), magnon junction effect (MJE), magnon blocking effect (MBE), magnon-mediated nonlocal spin Hall magnetoresistance (MNSMR), magnon-transfer torque (MTT) effect, and magnon resonant tunneling (MRT) effect, magnon skin effect (MSE) etc. existing in magnon junctions or magnon heterojunctions, have been summarized and their potential applications in memory and logic devices etc. are prospected, from which we can see a promising future for spintronics and magnonics beyond micro-electronics.

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Section: Main Progressmentioning

confidence: 99%

From microelectronics to spintronics and magnonics

Han¹,

Wan²,

Wu³

et al. 2022

Chinese Phys. B

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“…Figure 4(a) shows a three-terminal MTJ device. [23][24][25][26] The MTJ device stores a binary datum M as a resistance value R M . Thus, R H corresponds to M = 1 and R L corresponds to M = 0.…”

Section: Mtj Devicementioning

confidence: 99%

“…In Ref. 19, we have presented the basic idea of an NV-FPGA-based BCNN accelerator in which a magnetictunnel-junction (MTJ) device [20][21][22][23][24][25][26] is used for the nonvolatile storage element. The standby power reduction mechanism of the NV-FPGA is quite suitable for massively parallel architecture independent of the number of idle components.…”

Section: Introductionmentioning

confidence: 99%

Design of an energy-efficient binarized convolutional neural network accelerator using a nonvolatile field-programmable gate array with only-once-write shifting

Suzuki¹,

Oka²,

Hanyu³

2021

Jpn. J. Appl. Phys.

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This paper presents an energy-efficient hardware accelerator for binarized convolutional neural networks (BCNNs). In this BCNN accelerator, a data-shift operation becomes dominant to effectively control input/weight-data streams under limited memory bandwidth. A magnetic-tunnel-junction (MTJ)-based nonvolatile field-programmable gate array (NV-FPGA), where the amount of stored-data updating is minimized in a configurable logic block, is a well-suited hardware platform for implementing such a BCNN accelerator. Owing to the nonvolatile storage capability of the NV-FPGA, not only power consumption in the data-shift operation but also standby power consumption in the idle function block is reduced without losing internal data. It is demonstrated under 45 nm complementary metal–oxide–semiconductor/MTJ process technologies that the energy consumption of the proposed BCNN accelerator is 50.7% lower than that of a BCNN accelerator using a conventional static-random-access-memory-based FPGA.

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“…Recently, a spin-orbit-torque (SOT) device which has a 3terminal structure has become another attractive nonvolatile device [36], [37]. By employing the 3-terminal structure, the read property and the write property can be independently optimized which is quite useful for the circuit design [38], [39].…”

Section: Fpga Architecturementioning

confidence: 99%

“…Moreover, the use of HDL also makes it easy to consider how to manage the control sequence of the FPGA components including circuit configuration, power gating, and so on. As a typical design example, an NV-FPGA is designed under 55nm CMOS/100nm magnetic tunnel junction (MTJ) [33]- [39] technologies and evaluated its benefits compared to the CMOS-only FPGA.…”

Section: Introductionmentioning

confidence: 99%

Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow

Suzuki

Hanyu

2021

IEICE Trans. Inf. & Syst.

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A nonvolatile field-programmable gate array (NV-FPGA), where the circuit-configuration information still remains without power supply, offers a powerful solution against the standby power issue. In this paper, an NV-FPGA is proposed where the programmable logic and interconnect function blocks are described in a hardware description language and are pushed through a standard-cell-based design flow with nonvolatile flip-flops. The use of the standard-cell-based design flow makes it possible to migrate any arbitrary process technology and to perform architecturelevel simulation with physical information. As a typical example, the proposed NV-FPGA is designed under 55nm CMOS/100nm magnetic tunnel junction (MTJ) technologies, and the performance of the proposed NV-FPGA is evaluated in comparison with that of a CMOS-only volatile FPGA.

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Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage

Cited by 18 publications

References 0 publications

From microelectronics to spintronics and magnonics

From microelectronics to spintronics and magnonics

Design of an energy-efficient binarized convolutional neural network accelerator using a nonvolatile field-programmable gate array with only-once-write shifting

Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow

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