DVAFS: Trading computational accuracy for energy through dynamic-voltage-accuracy-frequency-scaling

Moons, Bert; Uytterhoeven, Roel; Dehaene, Wim; Verhelst, Marian

doi:10.23919/date.2017.7927038

Cited by 40 publications

(33 citation statements)

References 24 publications

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“…Let assume the same carry error (C i = C err ) in a propagating stage (P i = 1, else there would be no carry-chain perturbation). If another cut-back happens to guess the same faulty carry C err , it does not disrupt the normal propagation and the previous result holds (2). But if the carry cut happens in the opposite direction C err , it overrides (2) and reverses the carry error: the carry, that was false until now, comes back to the value of the expected addition.…”

Section: E Worst-case Error and Floating-point Precision 1) Error Prmentioning

confidence: 93%

“…Approximate computing has been investigated at different levels of abstraction, such as voltage-frequency-precision scaling at circuit level [2] or significance-driven computation at algorithmic level [3]. Another way consists in redesigning the architecture of digital circuits into an approximate version with smaller delay, silicon area or power consumption.…”

Section: Introductionmentioning

confidence: 99%

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Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

Camus

Cacciotti

Schlachter

et al. 2018

IEEE J. Emerg. Sel. Topics Circuits Syst.

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This paper introduces a novel method for designing approximate circuits by fabricating and exploiting false timing paths, i.e., critical paths that cannot be logically activated. This allows to strongly relax timing constraints while guaranteeing minimal and controlled behavioral change. This technique is applied to an approximate adder architecture, called the Carry CutBack Adder (CCBA), in which high-significance stages can cut the carry propagation chain at lower-significance positions. This lightweight approach prevents the logic activation of the carry chain, improving performance and energy efficiency while guaranteeing low worst-case errors. A design methodology is presented along with implementation, error optimization, and design-space minimization. The CCBA is proven capable of extremely high accuracy while displaying significant circuit savings. For a worst case precision of 99.999%, energy savings up to 36% are demonstrated compared with exact adders. Finally, an industry-oriented comparison of 32-bit approximate and truncated adders is carried out for mean and worst-case relative errors. The CCBA outperforms both state-of-the-art and truncated adders for high-accuracy and low-power circuits, confirming the interest of the proposed concept to help building highly-efficient approximate or precision-scalable hardware accelerators.

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Section: E Worst-case Error and Floating-point Precision 1) Error Prmentioning

confidence: 93%

Section: Introductionmentioning

confidence: 99%

Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

Camus

Cacciotti

Schlachter

et al. 2018

IEEE J. Emerg. Sel. Topics Circuits Syst.

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show abstract

“…One of the most popular approaches to obtain more energy efficient inference for neural networks is through custom hardware accelerators, targeting field-programmable gate arrays (FPGAs) [15,19,39] or application-specific integrated circuit (ASICs) [3,6,28,40]. These are custom-built architectures that optimize the most energy-intensive operations involved in the inference process (typically multiply-and-accumulate loops).…”

Section: Custom Hardware Designsmentioning

confidence: 99%

“…Different types of dynamic inference optimizations have been proposed in literature. Some researchers have developed "big/little" systems in which two NNs of different sizes and complexities are used depending on the input complexity [5,8,11,28]. Conditional [24] and hierarchical/staged [25][26][27] inference are other effective forms of dynamic optimization.…”

Section: Introductionmentioning

confidence: 99%

Sequence-To-Sequence Neural Networks Inference on Embedded Processors Using Dynamic Beam Search

2020

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Sequence-to-sequence deep neural networks have become the state of the art for a variety of machine learning applications, ranging from neural machine translation (NMT) to speech recognition. Many mobile and Internet of Things (IoT) applications would benefit from the ability of performing sequence-to-sequence inference directly in embedded devices, thereby reducing the amount of raw data transmitted to the cloud, and obtaining benefits in terms of response latency, energy consumption and security. However, due to the high computational complexity of these models, specific optimization techniques are needed to achieve acceptable performance and energy consumption on single-core embedded processors. In this paper, we present a new optimization technique called dynamic beam search, in which the inference complexity is tuned to the difficulty of the processed input sequence at runtime. Results based on measurements on a real embedded device, and on three state-of-the-art deep learning models, show that our method is able to reduce the inference time and energy by up to 25% without loss of accuracy.

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“…In order to obtain different levels of approximation, two main approaches are followed. The first approach include voltage over-scaling methods such as [15] where over-scaling can vastly decrease quality by its impact on MSB. The second approach propose transistor level or gate level design and implementation methods.…”

Section: Background a Approximate Computing Circuitsmentioning

confidence: 99%

Circuit Aware Approximate System Design With Case Studies in Image Processing and Neural Networks

Ayhan

Altun²

2019

IEEE Access

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This paper aims to exploit approximate computing units in image processing systems and artificial neural networks. For this purpose, a general design methodology is introduced, and approximationoriented architectures are developed for different applications. This paper proposes a method to compromise power/area efficiency of circuit-level design with accuracy supervision of system-level design. The proposed method selects approximate computational units that minimize the total computation cost, yet maintaining the ultimate performance. This is accomplished by formulating a linear programming problem, which can be solved by conventional linear programming solvers. Approximate computing units, such as multipliers, neurons, and convolution kernels, which are proposed by this paper, are suitable for power/area reduction through accuracy scaling. The formulation is demonstrated on applications in image processing, digital filters, and artificial neural networks. This way, the proposed technique and architectures are tested with different approximate computing units, as well as system-level requirement metrics, such as PSNR and classification performance. INDEX TERMS Approximate computing, artificial neural networks, field programmable gate arrays, high-level synthesis, image processing.

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DVAFS: Trading computational accuracy for energy through dynamic-voltage-accuracy-frequency-scaling

Cited by 40 publications

References 24 publications

Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

Sequence-To-Sequence Neural Networks Inference on Embedded Processors Using Dynamic Beam Search

Circuit Aware Approximate System Design With Case Studies in Image Processing and Neural Networks

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