Dynamic state-retention flipflop for fine-grained sleep-transistor scheme

Henzler, Stephan; Nirschi, T.; Pacha, C.; Spindler, Peter; Teichmann, Philip; Fulde, M.; Fischer, Jürgen; Eireiner, Matthias; Fischer, Tony; Georgakos, Georg; Berthold, J.; Schmitt‐Landsiedel, D.

doi:10.1109/esscir.2005.1541580

Cited by 4 publications

(4 citation statements)

References 4 publications

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“…Scan-based techniques, which are used for serially saving and restoring internal retention cells, also suffer from latency and energy overhead [8]. The State Retention Power Gating (SPRG) technique addresses the above-mentioned PG technique's limitations [9][10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

A New Physical Design Flow for a Selective State Retention Based Approach

Rabinowicz

Greenberg

2021

JLPEA

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This research presents a novel approach for physical design implementation aimed for a System on Chip (SoC) based on Selective State Retention techniques. Leakage current has become a dominant factor in Very Large Scale Integration (VLSI) design. Power Gating (PG) techniques were first developed to mitigate these leakage currents, but they result in longer SoC wake-up periods due to loss of state. The common State Retention Power Gating (SRPG) approach was developed to overcome the PG technique’s loss of state drawback. However, SRPG resulted in a costly expense of die area overhead due to the additional state retention logic required to keep the design state when power is gated. Moreover, the physical design implementation of SRPG presents additional wiring due to the extra power supply network and power-gating controls for the state retention logic. This results in increased implementation complexity for the physical design tools, and therefore increases runtime and limits the ability to handle large designs. Recently published works on Selective State Retention Power Gating (SSRPG) techniques allow reducing the total amount of retention logic and their leakage currents. Although the SSRPG approach mitigates the overhead area and power limitations of the conventional SRPG technique, still both SRPG and SSRPG approaches require a similar extra power grid network for the retention cells, and the effect of the selective approach on the complexity of the physical design has not been yet investigated. Therefore, this paper introduces further analysis of the physical design flow for the SSRPG design, which is required for optimal cell placement and power grid allocation. This significantly increases the potential routing area, which directly improves the convergence time of the Place and Route tools.

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Section: Introductionmentioning

confidence: 99%

A New Physical Design Flow for a Selective State Retention Based Approach

Rabinowicz

Greenberg

2021

JLPEA

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“…It is reported that more than 40% of total power can be due to the leakage currents [1][2][3][4][5][6]. In an idle circuit, leakage is the main source of power consumption.…”

Section: Introductionmentioning

confidence: 99%

“…Henzler et al propose a dynamic state retention flip-flop using fine-grained sleep transistor scheme. But the retention time is in the range of milliseconds [4]. The selfdata retention flip-flop proposed by Seomun and Shin uses virtual power rail to control the operation.…”

Section: Introductionmentioning

confidence: 99%

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A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

Fan

Dong

et al. 2014

Journal of Electrical and Computer Engineering

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With the scaling of technology process, leakage power becomes an increasing portion of total power. Power gating technology is an effective method to suppress the leakage power in VLSI design. When the power gating technique is applied in sequential circuits, such as flip-flops and latches, the data retention is necessary to store the circuit states. A low leakage autonomous data retention flip-flop (ADR-FF) is proposed in this paper.

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Design of low power pulsed flip-flop using sleep transistor scheme

Rao¹,

Rajendar²

2013

2013 2nd International Conference on Advances in Electrical Engineering (ICAEE)

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Dynamic state-retention flipflop for fine-grained sleep-transistor scheme

Cited by 4 publications

References 4 publications

A New Physical Design Flow for a Selective State Retention Based Approach

A New Physical Design Flow for a Selective State Retention Based Approach

A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

Design of low power pulsed flip-flop using sleep transistor scheme

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