DYNAMITE: an efficient automatic test pattern generation system for path delay faults

Fuchs, Karl Josef; Fink, F.; Schulz, Michael

doi:10.1109/43.88928

Cited by 145 publications

(46 citation statements)

References 13 publications

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“…The main purpose of using the DPT is to avoid explicit enumeration and sensitization of all structural paths that are candidates for the sensitizable longest path. Fuchs, Fink, and Schulz proposed a similar structure, called a path tree, 8 but its properties and purpose are different from those of the DPT. To describe DPT, we define a stem as a gate that has more than one fan-out branch, and a branch as a gate that has at least one input signal from a stem.…”

Section: Finding Sensitizable Critical Pathsmentioning

confidence: 99%

“…[7][8][9] Thus, to obtain superior clock skew schedules, we must find the sensitizable (true) maximum and minimum path delay for all pairs of flip-flops. Although there are numerous studies on identifying false paths 9 or sensitizable long paths, 10,11 none attempts to find the maximum and minimum delays of sensitizable paths between all possible flip-flop pairs.…”

Section: Finding Sensitizable Critical Pathsmentioning

confidence: 99%

See 1 more Smart Citation

Yield-Driven, False-Path-Aware Clock Skew Scheduling

Tsai

Baik

Cc-P

et al. 2005

IEEE Des. Test. Comput.

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SEMICONDUCTOR TECHNOLOGY ADVANCES have enabled designers to integrate more functionality in a single chip. As design complexity increases, many new design techniques are developed to optimize chip area and power consumption, as well as performance. Traditionally, yield improvement has been achieved through process improvement. However, in deep-submicron technologies, process variations are difficult to control. As a result, many design decisions significantly affect yield. Therefore, designers should consider yield-related issues during the design phase.Timing failure is a major cause of yield loss for highperformance circuits. Although designers have used clock skew scheduling to increase operation frequency, there is little research addressing its impact on yield. We propose a novel clock-skew-scheduling scheme that improves yield without sacrificing performance. The scheme achieves this by combining accurate path delay information using our efficient sensitizable-critical-path search algorithm and a proportional slack distribution heuristic. Our experimental results show substantial yield improvement in many of the ISCAS89 and ITC99 benchmark circuits, and in one case improvement is as high as 50%. Existing methodsIn a zero-skew design, the circuit's longest path delay limits the shortest clock period. Properly assigning clock arrival times to each sequential element or introducing clock skew at various storage elements can help operate a circuit at a higher clock frequency.1,2 Because timing failure is the major cause of yield loss, proper clock skew assignment for performance and yield is extremely important. Previous works attempted to reduce susceptibility to delay defects caused by process variations by finding a clock skew schedule that minimizes the number of paths with small slack.3,4 However, as we show in this article, these approaches might not always improve yield, and the researchers did not verify their results with a yield model. Clock period optimizationTo increase operation frequency, designers have adopted techniques such as circuit retiming and pipelining to balance path delays in different parts of the circuit. Because path delays usually cannot be perfectly balanced, the application of clock skew scheduling can further optimize the clock period.1-3 Figure 1a shows an example circuit with three flip-flops. The maximum and minimum path delays between FF i and FF j are D ij and d ij , respectively. CP is the clock period, and T setup and T hold are the FF setup and hold times. Without clock skew scheduling and with zero slack, this design will have CP = max{D ij } + T setup . For this example, the value of CP is 4 where T setup = T hold = 0. However, to determine the optimal clock period with clock skew scheduling, we first define the clock arrival time to FF i as T i and the clock skew between FF i and FF j as s ij = T i -T j . By absorbing the FF delays as part of the path delays, we can write the hold time and setup time constraints as Yield-Driven, False-Path-Aware Clock Skew Scheduling ...

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Section: Finding Sensitizable Critical Pathsmentioning

confidence: 99%

Section: Finding Sensitizable Critical Pathsmentioning

confidence: 99%

Yield-Driven, False-Path-Aware Clock Skew Scheduling

Tsai

Baik

Cc-P

et al. 2005

IEEE Des. Test. Comput.

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show abstract

“…Structural algorithms, e.g. [11], work directly on the circuit-structure and benefit from applying efficient implications procedures based on multiple-valued logics. These are typically applied to a subset of critical paths extracted by dedicated algorithms, e.g.…”

Section: Related Workmentioning

confidence: 99%

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics

Eggersglüβ

Fey

Glowatz³

et al. 2010

J Electron Test

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As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to detect small delay defects and to verify the correct temporal behavior of a circuit.In this article, MONSOON, an efficient SAT-based approach for generating non-robust and robust test patterns for path delay faults is presented. MONSOON handles tri-state elements and environmental constraints occurring in industrial practice using multiple-valued logics. Structural techniques increase the efficiency of the algorithm. A comparison with a state-of-the-art approach shows a significant speed-up. Experimental results for large industrial circuits demonstrates the feasibility and robustness of MONSOON.

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“…In a recent paper, Bose et al [2] derive a 23-value logic system for the test generation for multiple paths. Fuchs et a1 [5] introduce a 10-valued logic for robust and a three-valued logic for nonrobust test generation.…”

Section: A Nine-value Logic Systemmentioning

confidence: 99%

“…Fuchs et a1 use an extended multiple backtrace procedure and the concept of static and dynamic learning for path delay fault testing [5]. Non-enumerative methods for test generation and fault simulation of delay faults have recently appeared in the literature 19, 141.…”

Section: Introductionmentioning

confidence: 99%