Echo cancellation and applications

Murano, K.; Unagami, S.; Amano, F.

doi:10.1109/35.46671

Cited by 59 publications

(16 citation statements)

References 23 publications

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“…9, it is obtained by inserting an appropriate number of delays (m = 3, which corresponds to 3N in the up-sampled signal). The DLMS algorithm is implemented with delayed coefficient adaption (see (14)). …”

Section: Sequential Delayed Lms-based Adaptive Fir Filtermentioning

confidence: 99%

FPGA-Implementation of Parallel and Sequential Architectures for Adaptive Noise Cancelation

Bahoura

Ezzaidi

2011

Circuits Syst Signal Process

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This paper presents a FPGA-based rapid prototyping of an adaptive noise canceller (ANC) using XUP Virtex-II Pro development board and Xilinx System Generator. New parallel and sequential architectures of the ANC are proposed and successfully applied to remove noise from electrocardiogram and speech signals. The pipelined architecture were evaluated and compared to existing high-speed systems using objective measurement tests. By providing comparable filtering performances that of the parallel architectures, the proposed sequential system required fewer material resources.

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Section: Sequential Delayed Lms-based Adaptive Fir Filtermentioning

confidence: 99%

FPGA-Implementation of Parallel and Sequential Architectures for Adaptive Noise Cancelation

Bahoura

Ezzaidi

2011

Circuits Syst Signal Process

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“…1a [6,7]. The echo signal is modeled as the result of an unintended transmission path between the local transmitter and local receiver.…”

Section: Review Of Existing Echo Canceller Workmentioning

confidence: 99%

Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme

Chen

Hsu

Lai

et al. 2007

J Sign Process Syst Sign Image Video Technol

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Abstract. Echo canceller plays an important role in the full-duplex communication system. Conventional implementations of echo cancellers are often the adaptive transversal filter architectures due to the simplicity and robustness of stability and convergence. However, the conventional echo cancellers suffer from high cost problem especially when the response time of the echo is long. In this paper, a new cost-efficient architecture of echo cancellers, targeting on 10GBase-T Ethernet System, is presented. The proposed scheme inherits the concept of channel shortening which is widely employed in DSL systems. A shortened impulse response filter is implemented at the receiver to shorten the impulse response of the echo signal. Hence, the overall cost of echo cancellers can be reduced. We generalize the channel shortening architecture to a joint multi-channel shortening scheme. The joint multi-channel shortening architecture can be applied to multiple-input multiple-output wireline communication systems to further reduce both the cost of echo and near-end crosstalk (NEXT) cancellers. We apply the proposed scheme to 10GBase-T Ethernet system. The simulation results show that the proposed echo and NEXT cancellers can save up to 35% hardware cost compared to the conventional transversal implementations.

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“…scheme [2] [3] is that the echo canceller is an adaptive FIR to produce an echo replica. The received signal subtracts the echo replica to eliminate the echo interference.…”

Section: Conventional Echo Cancellationmentioning

confidence: 99%

A Shortened Impulse Response Filter (SIRF) Scheme for Cost-Effective Echo Canceller Design of 10GBase-T Ethernet System

Hsu

Chen

Jheng

et al. 2006

2006 IEEE Workshop on Signal Processing Systems Design and Implementation

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Abstract-IEEE 802.3an task force is now developing new Ethernet Standard-10GBase-T. Currently, most of the 10Gbps Ethernet is developed with fiber medium due to the fiber high bandwidth. However, the fiber and optical device cost are still too high to be popular. Therefore, our goal is to lower the 10GBase-T transceiver cost. We propose two new low cost 10GBase-T transceiver architectures. One is echo shortening. A Shortened Impulse Response Filter (SIRF) is used to shorten the echo impulse response to reduce the echo canceller cost. The other is joint shortening. The SIRF is used to jointly shorten impulse response of echo and NEXT. Moreover, compare with the conventional architecture, the cost saving of the proposed echo shortening and joint shortening architecture is 12% and 35% respectively.

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Echo cancellation and applications

Cited by 59 publications

References 23 publications

FPGA-Implementation of Parallel and Sequential Architectures for Adaptive Noise Cancelation

FPGA-Implementation of Parallel and Sequential Architectures for Adaptive Noise Cancelation

Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme

A Shortened Impulse Response Filter (SIRF) Scheme for Cost-Effective Echo Canceller Design of 10GBase-T Ethernet System

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